diff options
Diffstat (limited to 'src/cpu/simple/atomic.cc')
| -rw-r--r-- | src/cpu/simple/atomic.cc | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/src/cpu/simple/atomic.cc b/src/cpu/simple/atomic.cc index 3ce0ba172..045b0160f 100644 --- a/src/cpu/simple/atomic.cc +++ b/src/cpu/simple/atomic.cc @@ -322,7 +322,7 @@ AtomicSimpleCPU::read(Addr addr, T &data, unsigned flags) // Now do the access. if (fault == NoFault) { Packet pkt = Packet(req, - req->isLocked() ? MemCmd::LoadLockedReq : MemCmd::ReadReq, + req->isLlsc() ? MemCmd::LoadLockedReq : MemCmd::ReadReq, Packet::Broadcast); pkt.dataStatic(dataPtr); @@ -338,7 +338,7 @@ AtomicSimpleCPU::read(Addr addr, T &data, unsigned flags) assert(!pkt.isError()); - if (req->isLocked()) { + if (req->isLlsc()) { TheISA::handleLockedRead(thread, req); } } @@ -462,7 +462,7 @@ AtomicSimpleCPU::write(T data, Addr addr, unsigned flags, uint64_t *res) MemCmd cmd = MemCmd::WriteReq; // default bool do_access = true; // flag to suppress cache access - if (req->isLocked()) { + if (req->isLlsc()) { cmd = MemCmd::StoreCondReq; do_access = TheISA::handleLockedWrite(thread, req); } else if (req->isSwap()) { |