diff options
Diffstat (limited to 'src/cpu/simple/base.hh')
| -rw-r--r-- | src/cpu/simple/base.hh | 20 |
1 files changed, 20 insertions, 0 deletions
diff --git a/src/cpu/simple/base.hh b/src/cpu/simple/base.hh index f2e1b278a..8134465af 100644 --- a/src/cpu/simple/base.hh +++ b/src/cpu/simple/base.hh @@ -1,5 +1,6 @@ /* * Copyright (c) 2011-2012 ARM Limited + * Copyright (c) 2013 Advanced Micro Devices, Inc. * All rights reserved * * The license below extends only to copyright in the software and shall @@ -84,6 +85,7 @@ class BaseSimpleCPU : public BaseCPU typedef TheISA::MiscReg MiscReg; typedef TheISA::FloatReg FloatReg; typedef TheISA::FloatRegBits FloatRegBits; + typedef TheISA::CCReg CCReg; protected: Trace::InstRecord *traceData; @@ -231,6 +233,10 @@ class BaseSimpleCPU : public BaseCPU Stats::Scalar numFpRegReads; Stats::Scalar numFpRegWrites; + //number of condition code register file accesses + Stats::Scalar numCCRegReads; + Stats::Scalar numCCRegWrites; + // number of simulated memory references Stats::Scalar numMemRefs; Stats::Scalar numLoadInsts; @@ -307,6 +313,13 @@ class BaseSimpleCPU : public BaseCPU return thread->readFloatRegBits(reg_idx); } + CCReg readCCRegOperand(const StaticInst *si, int idx) + { + numCCRegReads++; + int reg_idx = si->srcRegIdx(idx) - TheISA::CC_Reg_Base; + return thread->readCCReg(reg_idx); + } + void setIntRegOperand(const StaticInst *si, int idx, uint64_t val) { numIntRegWrites++; @@ -328,6 +341,13 @@ class BaseSimpleCPU : public BaseCPU thread->setFloatRegBits(reg_idx, val); } + void setCCRegOperand(const StaticInst *si, int idx, CCReg val) + { + numCCRegWrites++; + int reg_idx = si->destRegIdx(idx) - TheISA::CC_Reg_Base; + thread->setCCReg(reg_idx, val); + } + bool readPredicate() { return thread->readPredicate(); } void setPredicate(bool val) { |