diff options
Diffstat (limited to 'src/cpu/simple/base.hh')
-rw-r--r-- | src/cpu/simple/base.hh | 351 |
1 files changed, 23 insertions, 328 deletions
diff --git a/src/cpu/simple/base.hh b/src/cpu/simple/base.hh index 2f7247010..c108cb986 100644 --- a/src/cpu/simple/base.hh +++ b/src/cpu/simple/base.hh @@ -1,5 +1,5 @@ /* - * Copyright (c) 2011-2012 ARM Limited + * Copyright (c) 2011-2012,2015 ARM Limited * Copyright (c) 2013 Advanced Micro Devices, Inc. * All rights reserved * @@ -79,57 +79,35 @@ namespace Trace { struct BaseSimpleCPUParams; class BPredUnit; +class SimpleExecContext; -class BaseSimpleCPU : public BaseCPU, public ExecContext +class BaseSimpleCPU : public BaseCPU { protected: - typedef TheISA::MiscReg MiscReg; - typedef TheISA::FloatReg FloatReg; - typedef TheISA::FloatRegBits FloatRegBits; - typedef TheISA::CCReg CCReg; - + ThreadID curThread; BPredUnit *branchPred; - protected: - Trace::InstRecord *traceData; - - inline void checkPcEventQueue() { - Addr oldpc, pc = thread->instAddr(); - do { - oldpc = pc; - system->pcEventQueue.service(tc); - pc = thread->instAddr(); - } while (oldpc != pc); - } - - public: - void wakeup(); - - void zero_fill_64(Addr addr) { - static int warned = 0; - if (!warned) { - warn ("WH64 is not implemented"); - warned = 1; - } - }; + void checkPcEventQueue(); + void swapActiveThread(); public: BaseSimpleCPU(BaseSimpleCPUParams *params); virtual ~BaseSimpleCPU(); - + void wakeup(); + virtual void init(); public: - /** SimpleThread object, provides all the architectural state. */ - SimpleThread *thread; + Trace::InstRecord *traceData; + CheckerCPU *checker; - /** ThreadContext object, provides an interface for external - * objects to modify this thread's state. - */ - ThreadContext *tc; + std::vector<SimpleExecContext*> threadInfo; + std::list<ThreadID> activeThreads; - CheckerCPU *checker; + /** Current instruction */ + TheISA::MachInst inst; + StaticInstPtr curStaticInst; + StaticInstPtr curMacroStaticInst; protected: - enum Status { Idle, Running, @@ -147,22 +125,8 @@ class BaseSimpleCPU : public BaseCPU, public ExecContext Status _status; public: - Addr dbg_vtophys(Addr addr); - bool interval_stats; - - // current instruction - TheISA::MachInst inst; - - StaticInstPtr curStaticInst; - StaticInstPtr curMacroStaticInst; - - //This is the offset from the current pc that fetch should be performed at - Addr fetchOffset; - //This flag says to stay at the current pc. This is useful for - //instructions which go beyond MachInst boundaries. - bool stayAtPC; void checkForInterrupts(); void setupFetchRequest(Request *req); @@ -178,289 +142,20 @@ class BaseSimpleCPU : public BaseCPU, public ExecContext virtual void startup(); - // number of simulated instructions - Counter numInst; - Counter startNumInst; - Stats::Scalar numInsts; - Counter numOp; - Counter startNumOp; - Stats::Scalar numOps; - - void countInst() - { - if (!curStaticInst->isMicroop() || curStaticInst->isLastMicroop()) { - numInst++; - numInsts++; - } - numOp++; - numOps++; - - system->totalNumInsts++; - thread->funcExeInst++; - } - - virtual Counter totalInsts() const - { - return numInst - startNumInst; - } - - virtual Counter totalOps() const - { - return numOp - startNumOp; - } - - //number of integer alu accesses - Stats::Scalar numIntAluAccesses; - - //number of float alu accesses - Stats::Scalar numFpAluAccesses; - - //number of function calls/returns - Stats::Scalar numCallsReturns; - - //conditional control instructions; - Stats::Scalar numCondCtrlInsts; - - //number of int instructions - Stats::Scalar numIntInsts; - - //number of float instructions - Stats::Scalar numFpInsts; - - //number of integer register file accesses - Stats::Scalar numIntRegReads; - Stats::Scalar numIntRegWrites; - - //number of float register file accesses - Stats::Scalar numFpRegReads; - Stats::Scalar numFpRegWrites; - - //number of condition code register file accesses - Stats::Scalar numCCRegReads; - Stats::Scalar numCCRegWrites; + virtual Fault readMem(Addr addr, uint8_t* data, unsigned size, + unsigned flags) = 0; - // number of simulated memory references - Stats::Scalar numMemRefs; - Stats::Scalar numLoadInsts; - Stats::Scalar numStoreInsts; + virtual Fault writeMem(uint8_t* data, unsigned size, Addr addr, + unsigned flags, uint64_t* res) = 0; - // number of idle cycles - Stats::Formula numIdleCycles; - - // number of busy cycles - Stats::Formula numBusyCycles; - - // number of simulated loads - Counter numLoad; - Counter startNumLoad; - - // number of idle cycles - Stats::Average notIdleFraction; - Stats::Formula idleFraction; - - // number of cycles stalled for I-cache responses - Stats::Scalar icacheStallCycles; - Counter lastIcacheStall; - - // number of cycles stalled for D-cache responses - Stats::Scalar dcacheStallCycles; - Counter lastDcacheStall; - - /// @{ - /// Total number of branches fetched - Stats::Scalar numBranches; - /// Number of branches predicted as taken - Stats::Scalar numPredictedBranches; - /// Number of misprediced branches - Stats::Scalar numBranchMispred; - /// @} - - // instruction mix histogram by OpClass - Stats::Vector statExecutedInstType; + void countInst(); + virtual Counter totalInsts() const; + virtual Counter totalOps() const; void serializeThread(CheckpointOut &cp, ThreadID tid) const M5_ATTR_OVERRIDE; void unserializeThread(CheckpointIn &cp, ThreadID tid) M5_ATTR_OVERRIDE; - // These functions are only used in CPU models that split - // effective address computation from the actual memory access. - void setEA(Addr EA) { panic("BaseSimpleCPU::setEA() not implemented\n"); } - Addr getEA() const { panic("BaseSimpleCPU::getEA() not implemented\n"); } - - // The register accessor methods provide the index of the - // instruction's operand (e.g., 0 or 1), not the architectural - // register index, to simplify the implementation of register - // renaming. We find the architectural register index by indexing - // into the instruction's own operand index table. Note that a - // raw pointer to the StaticInst is provided instead of a - // ref-counted StaticInstPtr to redice overhead. This is fine as - // long as these methods don't copy the pointer into any long-term - // storage (which is pretty hard to imagine they would have reason - // to do). - - IntReg readIntRegOperand(const StaticInst *si, int idx) - { - numIntRegReads++; - return thread->readIntReg(si->srcRegIdx(idx)); - } - - FloatReg readFloatRegOperand(const StaticInst *si, int idx) - { - numFpRegReads++; - int reg_idx = si->srcRegIdx(idx) - TheISA::FP_Reg_Base; - return thread->readFloatReg(reg_idx); - } - - FloatRegBits readFloatRegOperandBits(const StaticInst *si, int idx) - { - numFpRegReads++; - int reg_idx = si->srcRegIdx(idx) - TheISA::FP_Reg_Base; - return thread->readFloatRegBits(reg_idx); - } - - CCReg readCCRegOperand(const StaticInst *si, int idx) - { - numCCRegReads++; - int reg_idx = si->srcRegIdx(idx) - TheISA::CC_Reg_Base; - return thread->readCCReg(reg_idx); - } - - void setIntRegOperand(const StaticInst *si, int idx, IntReg val) - { - numIntRegWrites++; - thread->setIntReg(si->destRegIdx(idx), val); - } - - void setFloatRegOperand(const StaticInst *si, int idx, FloatReg val) - { - numFpRegWrites++; - int reg_idx = si->destRegIdx(idx) - TheISA::FP_Reg_Base; - thread->setFloatReg(reg_idx, val); - } - - void setFloatRegOperandBits(const StaticInst *si, int idx, - FloatRegBits val) - { - numFpRegWrites++; - int reg_idx = si->destRegIdx(idx) - TheISA::FP_Reg_Base; - thread->setFloatRegBits(reg_idx, val); - } - - void setCCRegOperand(const StaticInst *si, int idx, CCReg val) - { - numCCRegWrites++; - int reg_idx = si->destRegIdx(idx) - TheISA::CC_Reg_Base; - thread->setCCReg(reg_idx, val); - } - - bool readPredicate() { return thread->readPredicate(); } - void setPredicate(bool val) - { - thread->setPredicate(val); - if (traceData) { - traceData->setPredicate(val); - } - } - TheISA::PCState pcState() const { return thread->pcState(); } - void pcState(const TheISA::PCState &val) { thread->pcState(val); } - Addr instAddr() { return thread->instAddr(); } - Addr nextInstAddr() { return thread->nextInstAddr(); } - MicroPC microPC() { return thread->microPC(); } - - MiscReg readMiscRegNoEffect(int misc_reg) const - { - return thread->readMiscRegNoEffect(misc_reg); - } - - MiscReg readMiscReg(int misc_reg) - { - numIntRegReads++; - return thread->readMiscReg(misc_reg); - } - - void setMiscReg(int misc_reg, const MiscReg &val) - { - numIntRegWrites++; - return thread->setMiscReg(misc_reg, val); - } - - MiscReg readMiscRegOperand(const StaticInst *si, int idx) - { - numIntRegReads++; - int reg_idx = si->srcRegIdx(idx) - TheISA::Misc_Reg_Base; - return thread->readMiscReg(reg_idx); - } - - void setMiscRegOperand( - const StaticInst *si, int idx, const MiscReg &val) - { - numIntRegWrites++; - int reg_idx = si->destRegIdx(idx) - TheISA::Misc_Reg_Base; - return thread->setMiscReg(reg_idx, val); - } - - void demapPage(Addr vaddr, uint64_t asn) - { - thread->demapPage(vaddr, asn); - } - - void demapInstPage(Addr vaddr, uint64_t asn) - { - thread->demapInstPage(vaddr, asn); - } - - void demapDataPage(Addr vaddr, uint64_t asn) - { - thread->demapDataPage(vaddr, asn); - } - - unsigned int readStCondFailures() const { - return thread->readStCondFailures(); - } - - void setStCondFailures(unsigned int sc_failures) { - thread->setStCondFailures(sc_failures); - } - - MiscReg readRegOtherThread(int regIdx, ThreadID tid = InvalidThreadID) - { - panic("Simple CPU models do not support multithreaded " - "register access.\n"); - } - - void setRegOtherThread(int regIdx, MiscReg val, - ThreadID tid = InvalidThreadID) - { - panic("Simple CPU models do not support multithreaded " - "register access.\n"); - } - - //Fault CacheOp(uint8_t Op, Addr EA); - - Fault hwrei() { return thread->hwrei(); } - bool simPalCheck(int palFunc) { return thread->simPalCheck(palFunc); } - - void - syscall(int64_t callnum) - { - if (FullSystem) - panic("Syscall emulation isn't available in FS mode.\n"); - - thread->syscall(callnum); - } - - ThreadContext *tcBase() { return tc; } - - private: - TheISA::PCState pred_pc; - - public: - // monitor/mwait funtions - void armMonitor(Addr address) { BaseCPU::armMonitor(address); } - bool mwait(PacketPtr pkt) { return BaseCPU::mwait(pkt); } - void mwaitAtomic(ThreadContext *tc) - { return BaseCPU::mwaitAtomic(tc, thread->dtb); } - AddressMonitor *getAddrMonitor() { return BaseCPU::getCpuAddrMonitor(); } }; #endif // __CPU_SIMPLE_BASE_HH__ |