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-rw-r--r--src/cpu/simple/base.hh21
1 files changed, 11 insertions, 10 deletions
diff --git a/src/cpu/simple/base.hh b/src/cpu/simple/base.hh
index f382158dd..d13be2877 100644
--- a/src/cpu/simple/base.hh
+++ b/src/cpu/simple/base.hh
@@ -47,8 +47,11 @@
// forward declarations
#if FULL_SYSTEM
class Processor;
-class AlphaITB;
-class AlphaDTB;
+namespace TheISA
+{
+ class ITB;
+ class DTB;
+}
class MemObject;
class RemoteGDB;
@@ -94,8 +97,8 @@ class BaseSimpleCPU : public BaseCPU
struct Params : public BaseCPU::Params
{
#if FULL_SYSTEM
- AlphaITB *itb;
- AlphaDTB *dtb;
+ TheISA::ITB *itb;
+ TheISA::DTB *dtb;
#else
Process *process;
#endif
@@ -282,25 +285,23 @@ class BaseSimpleCPU : public BaseCPU
return thread->readMiscReg(misc_reg);
}
- MiscReg readMiscRegWithEffect(int misc_reg, Fault &fault)
+ MiscReg readMiscRegWithEffect(int misc_reg)
{
- return thread->readMiscRegWithEffect(misc_reg, fault);
+ return thread->readMiscRegWithEffect(misc_reg);
}
- Fault setMiscReg(int misc_reg, const MiscReg &val)
+ void setMiscReg(int misc_reg, const MiscReg &val)
{
return thread->setMiscReg(misc_reg, val);
}
- Fault setMiscRegWithEffect(int misc_reg, const MiscReg &val)
+ void setMiscRegWithEffect(int misc_reg, const MiscReg &val)
{
return thread->setMiscRegWithEffect(misc_reg, val);
}
#if FULL_SYSTEM
Fault hwrei() { return thread->hwrei(); }
- int readIntrFlag() { return thread->readIntrFlag(); }
- void setIntrFlag(int val) { thread->setIntrFlag(val); }
bool inPalMode() { return thread->inPalMode(); }
void ev5_trap(Fault fault) { fault->invoke(tc); }
bool simPalCheck(int palFunc) { return thread->simPalCheck(palFunc); }