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-rw-r--r--src/cpu/simple/base.hh32
1 files changed, 9 insertions, 23 deletions
diff --git a/src/cpu/simple/base.hh b/src/cpu/simple/base.hh
index 3535539d0..55dec5d53 100644
--- a/src/cpu/simple/base.hh
+++ b/src/cpu/simple/base.hh
@@ -47,7 +47,6 @@
#include "arch/predecoder.hh"
#include "base/statistics.hh"
-#include "config/full_system.hh"
#include "config/the_isa.hh"
#include "config/use_checker.hh"
#include "cpu/base.hh"
@@ -59,6 +58,7 @@
#include "mem/port.hh"
#include "mem/request.hh"
#include "sim/eventq.hh"
+#include "sim/full_system.hh"
#include "sim/system.hh"
#if USE_CHECKER
@@ -66,27 +66,18 @@
#endif
// forward declarations
-#if FULL_SYSTEM
-class Processor;
-namespace TheISA
-{
- class ITB;
- class DTB;
-}
+class Checkpoint;
class MemObject;
-
-#else
-
class Process;
-
-#endif // FULL_SYSTEM
+class Processor;
+class ThreadContext;
namespace TheISA
{
+ class DTB;
+ class ITB;
class Predecoder;
}
-class ThreadContext;
-class Checkpoint;
namespace Trace {
class InstRecord;
@@ -162,11 +153,9 @@ class BaseSimpleCPU : public BaseCPU
public:
-#if FULL_SYSTEM
Addr dbg_vtophys(Addr addr);
bool interval_stats;
-#endif
// current instruction
TheISA::MachInst inst;
@@ -420,19 +409,16 @@ class BaseSimpleCPU : public BaseCPU
//Fault CacheOp(uint8_t Op, Addr EA);
-#if FULL_SYSTEM
Fault hwrei() { return thread->hwrei(); }
bool simPalCheck(int palFunc) { return thread->simPalCheck(palFunc); }
-#endif
void
syscall(int64_t callnum)
{
-#if FULL_SYSTEM
- panic("Syscall emulation isn't available in FS mode.\n");
-#else
+ if (FullSystem)
+ panic("Syscall emulation isn't available in FS mode.\n");
+
thread->syscall(callnum);
-#endif
}
bool misspeculating() { return thread->misspeculating(); }