summaryrefslogtreecommitdiff
path: root/src/cpu/simple/base.hh
diff options
context:
space:
mode:
Diffstat (limited to 'src/cpu/simple/base.hh')
-rw-r--r--src/cpu/simple/base.hh16
1 files changed, 15 insertions, 1 deletions
diff --git a/src/cpu/simple/base.hh b/src/cpu/simple/base.hh
index 8134465af..ad672da6c 100644
--- a/src/cpu/simple/base.hh
+++ b/src/cpu/simple/base.hh
@@ -77,7 +77,7 @@ namespace Trace {
}
struct BaseSimpleCPUParams;
-
+class BPredUnit;
class BaseSimpleCPU : public BaseCPU
{
@@ -87,6 +87,8 @@ class BaseSimpleCPU : public BaseCPU
typedef TheISA::FloatRegBits FloatRegBits;
typedef TheISA::CCReg CCReg;
+ BPredUnit *branchPred;
+
protected:
Trace::InstRecord *traceData;
@@ -272,6 +274,15 @@ class BaseSimpleCPU : public BaseCPU
Stats::Scalar dcacheRetryCycles;
Counter lastDcacheRetry;
+ /// @{
+ /// Total number of branches fetched
+ Stats::Scalar numBranches;
+ /// Number of branches predicted as taken
+ Stats::Scalar numPredictedBranches;
+ /// Number of misprediced branches
+ Stats::Scalar numBranchMispred;
+ /// @}
+
void serializeThread(std::ostream &os, ThreadID tid);
void unserializeThread(Checkpoint *cp, const std::string &section,
ThreadID tid);
@@ -446,6 +457,9 @@ class BaseSimpleCPU : public BaseCPU
bool misspeculating() { return thread->misspeculating(); }
ThreadContext *tcBase() { return tc; }
+
+ private:
+ TheISA::PCState pred_pc;
};
#endif // __CPU_SIMPLE_BASE_HH__