diff options
Diffstat (limited to 'src/cpu/simple/timing.cc')
| -rw-r--r-- | src/cpu/simple/timing.cc | 12 |
1 files changed, 10 insertions, 2 deletions
diff --git a/src/cpu/simple/timing.cc b/src/cpu/simple/timing.cc index 7996a6ddd..366164e36 100644 --- a/src/cpu/simple/timing.cc +++ b/src/cpu/simple/timing.cc @@ -1,5 +1,5 @@ /* - * Copyright (c) 2010-2012 ARM Limited + * Copyright (c) 2010-2013 ARM Limited * All rights reserved * * The license below extends only to copyright in the software and shall @@ -96,6 +96,7 @@ TimingSimpleCPU::TimingSimpleCPU(TimingSimpleCPUParams *p) } + TimingSimpleCPU::~TimingSimpleCPU() { } @@ -273,7 +274,7 @@ TimingSimpleCPU::sendData(RequestPtr req, uint8_t *data, uint64_t *res, bool do_access = true; // flag to suppress cache access if (req->isLLSC()) { - do_access = TheISA::handleLockedWrite(thread, req); + do_access = TheISA::handleLockedWrite(thread, req, dcachePort.cacheBlockMask); } else if (req->isCondSwap()) { assert(res); req->setExtraData(*res); @@ -813,6 +814,13 @@ TimingSimpleCPU::completeDataAccess(PacketPtr pkt) advanceInst(fault); } +void +TimingSimpleCPU::DcachePort::recvTimingSnoopReq(PacketPtr pkt) +{ + TheISA::handleLockedSnoop(cpu->thread, pkt, cacheBlockMask); +} + + bool TimingSimpleCPU::DcachePort::recvTimingResp(PacketPtr pkt) { |