1 files changed, 6 insertions, 1 deletions

diff --git a/src/cpu/simple/timing.cc b/src/cpu/simple/timing.cc
index f57354d56..c38f2107f 100644
--- a/src/cpu/simple/timing.cc
+++ b/src/cpu/simple/timing.cc
@@ -185,6 +185,7 @@ TimingSimpleCPU::switchOut()
     assert(thread->microPC() == 0);
 
     updateCycleCounts();
+    updateCycleCounters(BaseCPU::CPU_STATE_ON);
 }
 
 
@@ -363,6 +364,7 @@ TimingSimpleCPU::translationFault(const Fault &fault)
     // fault may be NoFault in cases where a fault is suppressed,
     // for instance prefetches.
     updateCycleCounts();
+    updateCycleCounters(BaseCPU::CPU_STATE_ON);
 
     if (traceData) {
         // Since there was a fault, we shouldn't trace this instruction.
@@ -631,6 +633,7 @@ TimingSimpleCPU::fetch()
         completeIfetch(NULL);
 
         updateCycleCounts();
+        updateCycleCounters(BaseCPU::CPU_STATE_ON);
     }
 }
 
@@ -664,6 +667,7 @@ TimingSimpleCPU::sendFetch(const Fault &fault, RequestPtr req,
     }
 
     updateCycleCounts();
+    updateCycleCounters(BaseCPU::CPU_STATE_ON);
 }
 
 
@@ -721,6 +725,7 @@ TimingSimpleCPU::completeIfetch(PacketPtr pkt)
     _status = BaseSimpleCPU::Running;
 
     updateCycleCounts();
+    updateCycleCounters(BaseCPU::CPU_STATE_ON);
 
     if (pkt)
         pkt->req->setAccessLatency();
@@ -821,6 +826,7 @@ TimingSimpleCPU::completeDataAccess(PacketPtr pkt)
     pkt->req->setAccessLatency();
 
     updateCycleCounts();
+    updateCycleCounters(BaseCPU::CPU_STATE_ON);
 
     if (pkt->senderState) {
         SplitFragmentSenderState * send_state =
@@ -875,7 +881,6 @@ TimingSimpleCPU::updateCycleCounts()
     const Cycles delta(curCycle() - previousCycle);
 
     numCycles += delta;
-    ppCycles->notify(delta);
 
     previousCycle = curCycle();
 }