1 files changed, 31 insertions, 1 deletions

diff --git a/src/cpu/simple/timing.cc b/src/cpu/simple/timing.cc
index 88aa882e3..ad5c0e5d6 100644
--- a/src/cpu/simple/timing.cc
+++ b/src/cpu/simple/timing.cc
@@ -103,6 +103,7 @@ TimingSimpleCPU::TimingSimpleCPU(Params *p)
     ifetch_pkt = dcache_pkt = NULL;
     drainEvent = NULL;
     fetchEvent = NULL;
+    previousTick = 0;
     changeState(SimObject::Running);
 }
 
@@ -162,6 +163,7 @@ TimingSimpleCPU::resume()
     }
 
     changeState(SimObject::Running);
+    previousTick = curTick;
 }
 
 void
@@ -169,6 +171,7 @@ TimingSimpleCPU::switchOut()
 {
     assert(status() == Running || status() == Idle);
     _status = SwitchedOut;
+    numCycles += curTick - previousTick;
 
     // If we've been scheduled to resume but are then told to switch out,
     // we'll need to cancel it.
@@ -195,6 +198,23 @@ TimingSimpleCPU::takeOverFrom(BaseCPU *oldCPU)
     if (_status != Running) {
         _status = Idle;
     }
+
+    Port *peer;
+    if (icachePort.getPeer() == NULL) {
+        peer = oldCPU->getPort("icache_port")->getPeer();
+        icachePort.setPeer(peer);
+    } else {
+        peer = icachePort.getPeer();
+    }
+    peer->setPeer(&icachePort);
+
+    if (dcachePort.getPeer() == NULL) {
+        peer = oldCPU->getPort("dcache_port")->getPeer();
+        dcachePort.setPeer(peer);
+    } else {
+        peer = dcachePort.getPeer();
+    }
+    peer->setPeer(&dcachePort);
 }
 
 
@@ -429,6 +449,9 @@ TimingSimpleCPU::fetch()
         // fetch fault: advance directly to next instruction (fault handler)
         advanceInst(fault);
     }
+
+    numCycles += curTick - previousTick;
+    previousTick = curTick;
 }
 
 
@@ -459,6 +482,9 @@ TimingSimpleCPU::completeIfetch(Packet *pkt)
     delete pkt->req;
     delete pkt;
 
+    numCycles += curTick - previousTick;
+    previousTick = curTick;
+
     if (getState() == SimObject::Draining) {
         completeDrain();
         return;
@@ -538,6 +564,9 @@ TimingSimpleCPU::completeDataAccess(Packet *pkt)
     assert(_status == DcacheWaitResponse);
     _status = Running;
 
+    numCycles += curTick - previousTick;
+    previousTick = curTick;
+
     Fault fault = curStaticInst->completeAcc(pkt, this, traceData);
 
     if (pkt->isRead() && pkt->req->isLocked()) {
@@ -547,6 +576,8 @@ TimingSimpleCPU::completeDataAccess(Packet *pkt)
     delete pkt->req;
     delete pkt;
 
+    postExecute();
+
     if (getState() == SimObject::Draining) {
         advancePC(fault);
         completeDrain();
@@ -554,7 +585,6 @@ TimingSimpleCPU::completeDataAccess(Packet *pkt)
         return;
     }
 
-    postExecute();
     advanceInst(fault);
 }