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-rw-r--r--src/cpu/simple/timing.cc10
1 files changed, 8 insertions, 2 deletions
diff --git a/src/cpu/simple/timing.cc b/src/cpu/simple/timing.cc
index 366164e36..3b4f0e7d8 100644
--- a/src/cpu/simple/timing.cc
+++ b/src/cpu/simple/timing.cc
@@ -472,14 +472,20 @@ TimingSimpleCPU::writeMem(uint8_t *data, unsigned size,
Addr addr, unsigned flags, uint64_t *res)
{
uint8_t *newData = new uint8_t[size];
- memcpy(newData, data, size);
-
const int asid = 0;
const ThreadID tid = 0;
const Addr pc = thread->instAddr();
unsigned block_size = cacheLineSize();
BaseTLB::Mode mode = BaseTLB::Write;
+ if (data == NULL) {
+ assert(flags & Request::CACHE_BLOCK_ZERO);
+ // This must be a cache block cleaning request
+ memset(newData, 0, size);
+ } else {
+ memcpy(newData, data, size);
+ }
+
if (traceData) {
traceData->setAddr(addr);
}