diff options
Diffstat (limited to 'src/cpu/simple/timing.cc')
| -rw-r--r-- | src/cpu/simple/timing.cc | 14 |
1 files changed, 14 insertions, 0 deletions
diff --git a/src/cpu/simple/timing.cc b/src/cpu/simple/timing.cc index 046b2fe3b..1e1f43f7d 100644 --- a/src/cpu/simple/timing.cc +++ b/src/cpu/simple/timing.cc @@ -544,6 +544,10 @@ TimingSimpleCPU::completeIfetch(PacketPtr pkt) // keep an instruction count if (fault == NoFault) countInst(); + } else if (traceData) { + // If there was a fault, we shouldn't trace this instruction. + delete traceData; + traceData = NULL; } postExecute(); @@ -556,6 +560,11 @@ TimingSimpleCPU::completeIfetch(PacketPtr pkt) // keep an instruction count if (fault == NoFault) countInst(); + else if (traceData) { + // If there was a fault, we shouldn't trace this instruction. + delete traceData; + traceData = NULL; + } postExecute(); advanceInst(fault); @@ -628,6 +637,11 @@ TimingSimpleCPU::completeDataAccess(PacketPtr pkt) // keep an instruction count if (fault == NoFault) countInst(); + else if (traceData) { + // If there was a fault, we shouldn't trace this instruction. + delete traceData; + traceData = NULL; + } if (pkt->isRead() && pkt->isLocked()) { TheISA::handleLockedRead(thread, pkt->req); |