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-rw-r--r--src/cpu/simple/timing.cc2
1 files changed, 1 insertions, 1 deletions
diff --git a/src/cpu/simple/timing.cc b/src/cpu/simple/timing.cc
index 2cf7d584d..b86d4b2d7 100644
--- a/src/cpu/simple/timing.cc
+++ b/src/cpu/simple/timing.cc
@@ -766,7 +766,7 @@ TimingSimpleCPU::DcachePort::setPeer(Port *port)
#if FULL_SYSTEM
// Update the ThreadContext's memory ports (Functional/Virtual
// Ports)
- cpu->tcBase()->connectMemPorts();
+ cpu->tcBase()->connectMemPorts(cpu->tcBase());
#endif
}