1 files changed, 4 insertions, 10 deletions

diff --git a/src/cpu/simple/timing.cc b/src/cpu/simple/timing.cc
index fa7bb4f86..7698a588d 100644
--- a/src/cpu/simple/timing.cc
+++ b/src/cpu/simple/timing.cc
@@ -168,9 +168,7 @@ TimingSimpleCPU::resume()
             delete fetchEvent;
         }
 
-        fetchEvent =
-            new EventWrapper<TimingSimpleCPU, &TimingSimpleCPU::fetch>(this, false);
-        fetchEvent->schedule(nextCycle());
+        fetchEvent = new FetchEvent(this, nextCycle());
     }
 
     changeState(SimObject::Running);
@@ -224,9 +222,7 @@ TimingSimpleCPU::activateContext(int thread_num, int delay)
     _status = Running;
 
     // kick things off by initiating the fetch of the next instruction
-    fetchEvent =
-        new EventWrapper<TimingSimpleCPU, &TimingSimpleCPU::fetch>(this, false);
-    fetchEvent->schedule(nextCycle(curTick + cycles(delay)));
+    fetchEvent = new FetchEvent(this, nextCycle(curTick + cycles(delay)));
 }
 
 
@@ -564,8 +560,7 @@ TimingSimpleCPU::IcachePort::recvTiming(PacketPtr pkt)
 {
     if (pkt->isResponse()) {
         // delay processing of returned data until next CPU clock edge
-        Tick mem_time = pkt->req->getTime();
-        Tick next_tick = cpu->nextCycle(mem_time);
+        Tick next_tick = cpu->nextCycle(curTick);
 
         if (next_tick == curTick)
             cpu->completeIfetch(pkt);
@@ -659,8 +654,7 @@ TimingSimpleCPU::DcachePort::recvTiming(PacketPtr pkt)
 {
     if (pkt->isResponse()) {
         // delay processing of returned data until next CPU clock edge
-        Tick mem_time = pkt->req->getTime();
-        Tick next_tick = cpu->nextCycle(mem_time);
+        Tick next_tick = cpu->nextCycle(curTick);
 
         if (next_tick == curTick)
             cpu->completeDataAccess(pkt);