1 files changed, 36 insertions, 36 deletions

diff --git a/src/cpu/simple/timing.cc b/src/cpu/simple/timing.cc
index 70b88c4b1..7cdcdafa1 100644
--- a/src/cpu/simple/timing.cc
+++ b/src/cpu/simple/timing.cc
@@ -158,10 +158,11 @@ TimingSimpleCPU::suspendContext(int thread_num)
     assert(thread_num == 0);
     assert(cpuXC);
 
-    panic("TimingSimpleCPU::suspendContext not implemented");
-
     assert(_status == Running);
 
+    // just change status to Idle... if status != Running,
+    // completeInst() will not initiate fetch of next instruction.
+
     notIdleFraction--;
     _status = Idle;
 }
@@ -187,13 +188,9 @@ TimingSimpleCPU::read(Addr addr, T &data, unsigned flags)
 
     // Now do the access.
     if (fault == NoFault) {
-        Packet *data_read_pkt = new Packet;
-        data_read_pkt->cmd = Read;
-        data_read_pkt->req = data_read_req;
+        Packet *data_read_pkt =
+            new Packet(data_read_req, Packet::ReadReq, Packet::Broadcast);
         data_read_pkt->dataDynamic<T>(new T);
-        data_read_pkt->addr = data_read_req->getPaddr();
-        data_read_pkt->size = sizeof(T);
-        data_read_pkt->dest = Packet::Broadcast;
 
         if (!dcachePort.sendTiming(data_read_pkt)) {
             _status = DcacheRetry;
@@ -268,14 +265,10 @@ TimingSimpleCPU::write(T data, Addr addr, unsigned flags, uint64_t *res)
     Fault fault = cpuXC->translateDataWriteReq(data_write_req);
     // Now do the access.
     if (fault == NoFault) {
-        Packet *data_write_pkt = new Packet;
-        data_write_pkt->cmd = Write;
-        data_write_pkt->req = data_write_req;
+        Packet *data_write_pkt =
+            new Packet(data_write_req, Packet::WriteReq, Packet::Broadcast);
         data_write_pkt->allocate();
-        data_write_pkt->size = sizeof(T);
         data_write_pkt->set(data);
-        data_write_pkt->addr = data_write_req->getPaddr();
-        data_write_pkt->dest = Packet::Broadcast;
 
         if (!dcachePort.sendTiming(data_write_pkt)) {
             _status = DcacheRetry;
@@ -350,12 +343,8 @@ TimingSimpleCPU::fetch()
     Request *ifetch_req = new Request(true);
     ifetch_req->setSize(sizeof(MachInst));
 
-    ifetch_pkt = new Packet;
-    ifetch_pkt->cmd = Read;
+    ifetch_pkt = new Packet(ifetch_req, Packet::ReadReq, Packet::Broadcast);
     ifetch_pkt->dataStatic(&inst);
-    ifetch_pkt->req = ifetch_req;
-    ifetch_pkt->size = sizeof(MachInst);
-    ifetch_pkt->dest = Packet::Broadcast;
 
     Fault fault = setupFetchPacket(ifetch_pkt);
     if (fault == NoFault) {
@@ -369,20 +358,15 @@ TimingSimpleCPU::fetch()
             ifetch_pkt = NULL;
         }
     } else {
-        panic("TimingSimpleCPU fetch fault handling not implemented");
+        // fetch fault: advance directly to next instruction (fault handler)
+        advanceInst(fault);
     }
 }
 
 
 void
-TimingSimpleCPU::completeInst(Fault fault)
+TimingSimpleCPU::advanceInst(Fault fault)
 {
-    postExecute();
-
-    if (traceData) {
-        traceData->finalize();
-    }
-
     advancePC(fault);
 
     if (_status == Running) {
@@ -395,23 +379,35 @@ TimingSimpleCPU::completeInst(Fault fault)
 
 
 void
-TimingSimpleCPU::completeIfetch()
+TimingSimpleCPU::completeIfetch(Packet *pkt)
 {
     // received a response from the icache: execute the received
     // instruction
+    assert(pkt->result == Packet::Success);
     assert(_status == IcacheWaitResponse);
     _status = Running;
+
+    delete pkt->req;
+    delete pkt;
+
     preExecute();
-    if (curStaticInst->isMemRef()) {
+    if (curStaticInst->isMemRef() && !curStaticInst->isDataPrefetch()) {
         // load or store: just send to dcache
         Fault fault = curStaticInst->initiateAcc(this, traceData);
-        assert(fault == NoFault);
-        assert(_status == DcacheWaitResponse);
-        // instruction will complete in dcache response callback
+        if (fault == NoFault) {
+            // successfully initiated access: instruction will
+            // complete in dcache response callback
+            assert(_status == DcacheWaitResponse);
+        } else {
+            // fault: complete now to invoke fault handler
+            postExecute();
+            advanceInst(fault);
+        }
     } else {
         // non-memory instruction: execute completely now
         Fault fault = curStaticInst->execute(this, traceData);
-        completeInst(fault);
+        postExecute();
+        advanceInst(fault);
     }
 }
 
@@ -419,7 +415,7 @@ TimingSimpleCPU::completeIfetch()
 bool
 TimingSimpleCPU::IcachePort::recvTiming(Packet *pkt)
 {
-    cpu->completeIfetch();
+    cpu->completeIfetch(pkt);
     return true;
 }
 
@@ -441,13 +437,17 @@ TimingSimpleCPU::completeDataAccess(Packet *pkt)
 {
     // received a response from the dcache: complete the load or store
     // instruction
-    assert(pkt->result == Success);
+    assert(pkt->result == Packet::Success);
     assert(_status == DcacheWaitResponse);
     _status = Running;
 
     Fault fault = curStaticInst->completeAcc(pkt, this, traceData);
 
-    completeInst(fault);
+    delete pkt->req;
+    delete pkt;
+
+    postExecute();
+    advanceInst(fault);
 }