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-rw-r--r--src/cpu/simple/timing.cc6
1 files changed, 4 insertions, 2 deletions
diff --git a/src/cpu/simple/timing.cc b/src/cpu/simple/timing.cc
index 075d05d81..744bf8397 100644
--- a/src/cpu/simple/timing.cc
+++ b/src/cpu/simple/timing.cc
@@ -143,8 +143,10 @@ TimingSimpleCPU::drainResume()
if (thread->status() == ThreadContext::Active) {
schedule(fetchEvent, nextCycle());
_status = BaseSimpleCPU::Running;
+ notIdleFraction = 1;
} else {
_status = BaseSimpleCPU::Idle;
+ notIdleFraction = 0;
}
}
@@ -206,7 +208,7 @@ TimingSimpleCPU::activateContext(ThreadID thread_num, Cycles delay)
assert(_status == Idle);
- notIdleFraction++;
+ notIdleFraction = 1;
_status = BaseSimpleCPU::Running;
// kick things off by initiating the fetch of the next instruction
@@ -230,7 +232,7 @@ TimingSimpleCPU::suspendContext(ThreadID thread_num)
// just change status to Idle... if status != Running,
// completeInst() will not initiate fetch of next instruction.
- notIdleFraction--;
+ notIdleFraction = 0;
_status = Idle;
}