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Diffstat (limited to 'src/cpu/simple/timing.cc')
-rw-r--r--src/cpu/simple/timing.cc18
1 files changed, 8 insertions, 10 deletions
diff --git a/src/cpu/simple/timing.cc b/src/cpu/simple/timing.cc
index f8d13efd9..fd02e8300 100644
--- a/src/cpu/simple/timing.cc
+++ b/src/cpu/simple/timing.cc
@@ -54,6 +54,7 @@
#include "mem/packet_access.hh"
#include "params/TimingSimpleCPU.hh"
#include "sim/faults.hh"
+#include "sim/full_system.hh"
#include "sim/system.hh"
using namespace std;
@@ -74,17 +75,16 @@ void
TimingSimpleCPU::init()
{
BaseCPU::init();
-#if FULL_SYSTEM
- for (int i = 0; i < threadContexts.size(); ++i) {
- ThreadContext *tc = threadContexts[i];
-
- // initialize CPU, including PC
- TheISA::initCPU(tc, _cpuId);
+ if (FullSystem) {
+ for (int i = 0; i < threadContexts.size(); ++i) {
+ ThreadContext *tc = threadContexts[i];
+ // initialize CPU, including PC
+ TheISA::initCPU(tc, _cpuId);
+ }
}
// Initialise the ThreadContext's memory proxies
tcBase()->initMemProxies(tcBase());
-#endif
}
void
@@ -966,9 +966,7 @@ TimingSimpleCPU *
TimingSimpleCPUParams::create()
{
numThreads = 1;
-#if !FULL_SYSTEM
- if (workload.size() != 1)
+ if (!FullSystem && workload.size() != 1)
panic("only one workload allowed");
-#endif
return new TimingSimpleCPU(this);
}