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-rw-r--r--src/cpu/simple/timing.cc4
1 files changed, 2 insertions, 2 deletions
diff --git a/src/cpu/simple/timing.cc b/src/cpu/simple/timing.cc
index 1f453ca63..87a5245b2 100644
--- a/src/cpu/simple/timing.cc
+++ b/src/cpu/simple/timing.cc
@@ -404,7 +404,7 @@ TimingSimpleCPU::readMem(Addr addr, uint8_t *data,
const int asid = 0;
const ThreadID tid = 0;
const Addr pc = thread->instAddr();
- unsigned block_size = dcachePort.peerBlockSize();
+ unsigned block_size = cacheLineSize();
BaseTLB::Mode mode = BaseTLB::Read;
if (traceData) {
@@ -473,7 +473,7 @@ TimingSimpleCPU::writeMem(uint8_t *data, unsigned size,
const int asid = 0;
const ThreadID tid = 0;
const Addr pc = thread->instAddr();
- unsigned block_size = dcachePort.peerBlockSize();
+ unsigned block_size = cacheLineSize();
BaseTLB::Mode mode = BaseTLB::Write;
if (traceData) {