diff options
Diffstat (limited to 'src/cpu/simple/timing.cc')
| -rw-r--r-- | src/cpu/simple/timing.cc | 16 |
1 files changed, 11 insertions, 5 deletions
diff --git a/src/cpu/simple/timing.cc b/src/cpu/simple/timing.cc index fc35f2666..9fe3d2fff 100644 --- a/src/cpu/simple/timing.cc +++ b/src/cpu/simple/timing.cc @@ -598,13 +598,19 @@ TimingSimpleCPU::completeIfetch(PacketPtr pkt) assert(fault == NoFault); } else { if (fault == NoFault) { + // Note that ARM can have NULL packets if the instruction gets + // squashed due to predication // early fail on store conditional: complete now - assert(dcache_pkt != NULL); + assert(dcache_pkt != NULL || THE_ISA == ARM_ISA); + fault = curStaticInst->completeAcc(dcache_pkt, this, traceData); - delete dcache_pkt->req; - delete dcache_pkt; - dcache_pkt = NULL; + if (dcache_pkt != NULL) + { + delete dcache_pkt->req; + delete dcache_pkt; + dcache_pkt = NULL; + } // keep an instruction count if (fault == NoFault) @@ -816,7 +822,7 @@ TimingSimpleCPU::IprEvent::process() } const char * -TimingSimpleCPU::IprEvent::description() +TimingSimpleCPU::IprEvent::description() const { return "Timing Simple CPU Delay IPR event"; } |