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Diffstat (limited to 'src/cpu/simple/timing.cc')
-rw-r--r--src/cpu/simple/timing.cc12
1 files changed, 6 insertions, 6 deletions
diff --git a/src/cpu/simple/timing.cc b/src/cpu/simple/timing.cc
index 64c4108a7..905acb6d4 100644
--- a/src/cpu/simple/timing.cc
+++ b/src/cpu/simple/timing.cc
@@ -290,7 +290,7 @@ TimingSimpleCPU::sendData(Fault fault, RequestPtr req,
} else {
bool do_access = true; // flag to suppress cache access
- if (req->isLocked()) {
+ if (req->isLlsc()) {
do_access = TheISA::handleLockedWrite(thread, req);
} else if (req->isCondSwap()) {
assert(res);
@@ -384,11 +384,11 @@ TimingSimpleCPU::buildPacket(PacketPtr &pkt, RequestPtr req, bool read)
MemCmd cmd;
if (read) {
cmd = MemCmd::ReadReq;
- if (req->isLocked())
+ if (req->isLlsc())
cmd = MemCmd::LoadLockedReq;
} else {
cmd = MemCmd::WriteReq;
- if (req->isLocked()) {
+ if (req->isLlsc()) {
cmd = MemCmd::StoreCondReq;
} else if (req->isSwap()) {
cmd = MemCmd::SwapReq;
@@ -452,7 +452,7 @@ TimingSimpleCPU::read(Addr addr, T &data, unsigned flags)
_status = DTBWaitResponse;
if (split_addr > addr) {
RequestPtr req1, req2;
- assert(!req->isLocked() && !req->isSwap());
+ assert(!req->isLlsc() && !req->isSwap());
req->splitOnVaddr(split_addr, req1, req2);
typedef SplitDataTranslation::WholeTranslationState WholeState;
@@ -571,7 +571,7 @@ TimingSimpleCPU::write(T data, Addr addr, unsigned flags, uint64_t *res)
_status = DTBWaitResponse;
if (split_addr > addr) {
RequestPtr req1, req2;
- assert(!req->isLocked() && !req->isSwap());
+ assert(!req->isLlsc() && !req->isSwap());
req->splitOnVaddr(split_addr, req1, req2);
typedef SplitDataTranslation::WholeTranslationState WholeState;
@@ -904,7 +904,7 @@ TimingSimpleCPU::completeDataAccess(PacketPtr pkt)
// the locked flag may be cleared on the response packet, so check
// pkt->req and not pkt to see if it was a load-locked
- if (pkt->isRead() && pkt->req->isLocked()) {
+ if (pkt->isRead() && pkt->req->isLlsc()) {
TheISA::handleLockedRead(thread, pkt->req);
}