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-rw-r--r--src/cpu/simple/atomic.cc10
-rw-r--r--src/cpu/simple/atomic.hh18
-rw-r--r--src/cpu/simple/timing.cc20
-rw-r--r--src/cpu/simple/timing.hh20
4 files changed, 34 insertions, 34 deletions
diff --git a/src/cpu/simple/atomic.cc b/src/cpu/simple/atomic.cc
index fcda974e3..38a8ba097 100644
--- a/src/cpu/simple/atomic.cc
+++ b/src/cpu/simple/atomic.cc
@@ -93,21 +93,21 @@ AtomicSimpleCPU::init()
}
bool
-AtomicSimpleCPU::CpuPort::recvTiming(Packet *pkt)
+AtomicSimpleCPU::CpuPort::recvTiming(PacketPtr pkt)
{
panic("AtomicSimpleCPU doesn't expect recvTiming callback!");
return true;
}
Tick
-AtomicSimpleCPU::CpuPort::recvAtomic(Packet *pkt)
+AtomicSimpleCPU::CpuPort::recvAtomic(PacketPtr pkt)
{
//Snooping a coherence request, just return
return curTick;
}
void
-AtomicSimpleCPU::CpuPort::recvFunctional(Packet *pkt)
+AtomicSimpleCPU::CpuPort::recvFunctional(PacketPtr pkt)
{
//No internal storage to update, just return
return;
@@ -260,7 +260,7 @@ AtomicSimpleCPU::read(Addr addr, T &data, unsigned flags)
{
// use the CPU's statically allocated read request and packet objects
Request *req = data_read_req;
- Packet *pkt = data_read_pkt;
+ PacketPtr pkt = data_read_pkt;
req->setVirt(0, addr, sizeof(T), flags, thread->readPC());
@@ -342,7 +342,7 @@ AtomicSimpleCPU::write(T data, Addr addr, unsigned flags, uint64_t *res)
{
// use the CPU's statically allocated write request and packet objects
Request *req = data_write_req;
- Packet *pkt = data_write_pkt;
+ PacketPtr pkt = data_write_pkt;
req->setVirt(0, addr, sizeof(T), flags, thread->readPC());
diff --git a/src/cpu/simple/atomic.hh b/src/cpu/simple/atomic.hh
index 52afd76ef..0edca9369 100644
--- a/src/cpu/simple/atomic.hh
+++ b/src/cpu/simple/atomic.hh
@@ -92,11 +92,11 @@ class AtomicSimpleCPU : public BaseSimpleCPU
protected:
- virtual bool recvTiming(Packet *pkt);
+ virtual bool recvTiming(PacketPtr pkt);
- virtual Tick recvAtomic(Packet *pkt);
+ virtual Tick recvAtomic(PacketPtr pkt);
- virtual void recvFunctional(Packet *pkt);
+ virtual void recvFunctional(PacketPtr pkt);
virtual void recvStatusChange(Status status);
@@ -110,12 +110,12 @@ class AtomicSimpleCPU : public BaseSimpleCPU
CpuPort icachePort;
CpuPort dcachePort;
- Request *ifetch_req;
- Packet *ifetch_pkt;
- Request *data_read_req;
- Packet *data_read_pkt;
- Request *data_write_req;
- Packet *data_write_pkt;
+ Request *ifetch_req;
+ PacketPtr ifetch_pkt;
+ Request *data_read_req;
+ PacketPtr data_read_pkt;
+ Request *data_write_req;
+ PacketPtr data_write_pkt;
bool dcache_access;
Tick dcache_latency;
diff --git a/src/cpu/simple/timing.cc b/src/cpu/simple/timing.cc
index 3ddc938c3..97df0e5d5 100644
--- a/src/cpu/simple/timing.cc
+++ b/src/cpu/simple/timing.cc
@@ -66,14 +66,14 @@ TimingSimpleCPU::init()
}
Tick
-TimingSimpleCPU::CpuPort::recvAtomic(Packet *pkt)
+TimingSimpleCPU::CpuPort::recvAtomic(PacketPtr pkt)
{
panic("TimingSimpleCPU doesn't expect recvAtomic callback!");
return curTick;
}
void
-TimingSimpleCPU::CpuPort::recvFunctional(Packet *pkt)
+TimingSimpleCPU::CpuPort::recvFunctional(PacketPtr pkt)
{
//No internal storage to update, jusst return
return;
@@ -90,7 +90,7 @@ TimingSimpleCPU::CpuPort::recvStatusChange(Status status)
void
-TimingSimpleCPU::CpuPort::TickEvent::schedule(Packet *_pkt, Tick t)
+TimingSimpleCPU::CpuPort::TickEvent::schedule(PacketPtr _pkt, Tick t)
{
pkt = _pkt;
Event::schedule(t);
@@ -269,7 +269,7 @@ TimingSimpleCPU::read(Addr addr, T &data, unsigned flags)
// Now do the access.
if (fault == NoFault) {
- Packet *pkt =
+ PacketPtr pkt =
new Packet(req, Packet::ReadReq, Packet::Broadcast);
pkt->dataDynamic<T>(new T);
@@ -471,7 +471,7 @@ TimingSimpleCPU::advanceInst(Fault fault)
void
-TimingSimpleCPU::completeIfetch(Packet *pkt)
+TimingSimpleCPU::completeIfetch(PacketPtr pkt)
{
// received a response from the icache: execute the received
// instruction
@@ -527,7 +527,7 @@ TimingSimpleCPU::IcachePort::ITickEvent::process()
}
bool
-TimingSimpleCPU::IcachePort::recvTiming(Packet *pkt)
+TimingSimpleCPU::IcachePort::recvTiming(PacketPtr pkt)
{
if (pkt->isResponse()) {
// delay processing of returned data until next CPU clock edge
@@ -555,7 +555,7 @@ TimingSimpleCPU::IcachePort::recvRetry()
// waiting to transmit
assert(cpu->ifetch_pkt != NULL);
assert(cpu->_status == IcacheRetry);
- Packet *tmp = cpu->ifetch_pkt;
+ PacketPtr tmp = cpu->ifetch_pkt;
if (sendTiming(tmp)) {
cpu->_status = IcacheWaitResponse;
cpu->ifetch_pkt = NULL;
@@ -563,7 +563,7 @@ TimingSimpleCPU::IcachePort::recvRetry()
}
void
-TimingSimpleCPU::completeDataAccess(Packet *pkt)
+TimingSimpleCPU::completeDataAccess(PacketPtr pkt)
{
// received a response from the dcache: complete the load or store
// instruction
@@ -605,7 +605,7 @@ TimingSimpleCPU::completeDrain()
}
bool
-TimingSimpleCPU::DcachePort::recvTiming(Packet *pkt)
+TimingSimpleCPU::DcachePort::recvTiming(PacketPtr pkt)
{
if (pkt->isResponse()) {
// delay processing of returned data until next CPU clock edge
@@ -639,7 +639,7 @@ TimingSimpleCPU::DcachePort::recvRetry()
// waiting to transmit
assert(cpu->dcache_pkt != NULL);
assert(cpu->_status == DcacheRetry);
- Packet *tmp = cpu->dcache_pkt;
+ PacketPtr tmp = cpu->dcache_pkt;
if (sendTiming(tmp)) {
cpu->_status = DcacheWaitResponse;
// memory system takes ownership of packet
diff --git a/src/cpu/simple/timing.hh b/src/cpu/simple/timing.hh
index 988ddeded..577e13e40 100644
--- a/src/cpu/simple/timing.hh
+++ b/src/cpu/simple/timing.hh
@@ -84,9 +84,9 @@ class TimingSimpleCPU : public BaseSimpleCPU
protected:
- virtual Tick recvAtomic(Packet *pkt);
+ virtual Tick recvAtomic(PacketPtr pkt);
- virtual void recvFunctional(Packet *pkt);
+ virtual void recvFunctional(PacketPtr pkt);
virtual void recvStatusChange(Status status);
@@ -96,13 +96,13 @@ class TimingSimpleCPU : public BaseSimpleCPU
struct TickEvent : public Event
{
- Packet *pkt;
+ PacketPtr pkt;
TimingSimpleCPU *cpu;
TickEvent(TimingSimpleCPU *_cpu)
:Event(&mainEventQueue), cpu(_cpu) {}
const char *description() { return "Timing CPU clock event"; }
- void schedule(Packet *_pkt, Tick t);
+ void schedule(PacketPtr _pkt, Tick t);
};
};
@@ -117,7 +117,7 @@ class TimingSimpleCPU : public BaseSimpleCPU
protected:
- virtual bool recvTiming(Packet *pkt);
+ virtual bool recvTiming(PacketPtr pkt);
virtual void recvRetry();
@@ -144,7 +144,7 @@ class TimingSimpleCPU : public BaseSimpleCPU
protected:
- virtual bool recvTiming(Packet *pkt);
+ virtual bool recvTiming(PacketPtr pkt);
virtual void recvRetry();
@@ -163,8 +163,8 @@ class TimingSimpleCPU : public BaseSimpleCPU
IcachePort icachePort;
DcachePort dcachePort;
- Packet *ifetch_pkt;
- Packet *dcache_pkt;
+ PacketPtr ifetch_pkt;
+ PacketPtr dcache_pkt;
int cpu_id;
Tick previousTick;
@@ -192,8 +192,8 @@ class TimingSimpleCPU : public BaseSimpleCPU
Fault write(T data, Addr addr, unsigned flags, uint64_t *res);
void fetch();
- void completeIfetch(Packet *);
- void completeDataAccess(Packet *);
+ void completeIfetch(PacketPtr );
+ void completeDataAccess(PacketPtr );
void advanceInst(Fault fault);
private:
void completeDrain();
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-11 07:37:20 +0000