3 files changed, 13 insertions, 121 deletions

diff --git a/src/cpu/simple/base.cc b/src/cpu/simple/base.cc
index 196b72cc0..c993110e1 100644
--- a/src/cpu/simple/base.cc
+++ b/src/cpu/simple/base.cc
@@ -215,118 +215,6 @@ change_thread_state(ThreadID tid, int activate, int priority)
 {
 }
 
-void
-BaseSimpleCPU::prefetch(Addr addr, unsigned flags)
-{
-    if (traceData) {
-        traceData->setAddr(addr);
-    }
-
-    // need to do this...
-}
-
-void
-BaseSimpleCPU::writeHint(Addr addr, int size, unsigned flags)
-{
-    if (traceData) {
-        traceData->setAddr(addr);
-    }
-
-    // need to do this...
-}
-
-
-Fault
-BaseSimpleCPU::copySrcTranslate(Addr src)
-{
-#if 0
-    static bool no_warn = true;
-    unsigned blk_size =
-        (dcacheInterface) ? dcacheInterface->getBlockSize() : 64;
-    // Only support block sizes of 64 atm.
-    assert(blk_size == 64);
-    int offset = src & (blk_size - 1);
-
-    // Make sure block doesn't span page
-    if (no_warn &&
-        (src & PageMask) != ((src + blk_size) & PageMask) &&
-        (src >> 40) != 0xfffffc) {
-        warn("Copied block source spans pages %x.", src);
-        no_warn = false;
-    }
-
-    memReq->reset(src & ~(blk_size - 1), blk_size);
-
-    // translate to physical address
-    Fault fault = thread->translateDataReadReq(req);
-
-    if (fault == NoFault) {
-        thread->copySrcAddr = src;
-        thread->copySrcPhysAddr = memReq->paddr + offset;
-    } else {
-        assert(!fault->isAlignmentFault());
-
-        thread->copySrcAddr = 0;
-        thread->copySrcPhysAddr = 0;
-    }
-    return fault;
-#else
-    return NoFault;
-#endif
-}
-
-Fault
-BaseSimpleCPU::copy(Addr dest)
-{
-#if 0
-    static bool no_warn = true;
-    unsigned blk_size =
-        (dcacheInterface) ? dcacheInterface->getBlockSize() : 64;
-    // Only support block sizes of 64 atm.
-    assert(blk_size == 64);
-    uint8_t data[blk_size];
-    //assert(thread->copySrcAddr);
-    int offset = dest & (blk_size - 1);
-
-    // Make sure block doesn't span page
-    if (no_warn &&
-        (dest & PageMask) != ((dest + blk_size) & PageMask) &&
-        (dest >> 40) != 0xfffffc) {
-        no_warn = false;
-        warn("Copied block destination spans pages %x. ", dest);
-    }
-
-    memReq->reset(dest & ~(blk_size -1), blk_size);
-    // translate to physical address
-    Fault fault = thread->translateDataWriteReq(req);
-
-    if (fault == NoFault) {
-        Addr dest_addr = memReq->paddr + offset;
-        // Need to read straight from memory since we have more than 8 bytes.
-        memReq->paddr = thread->copySrcPhysAddr;
-        thread->mem->read(memReq, data);
-        memReq->paddr = dest_addr;
-        thread->mem->write(memReq, data);
-        if (dcacheInterface) {
-            memReq->cmd = Copy;
-            memReq->completionEvent = NULL;
-            memReq->paddr = thread->copySrcPhysAddr;
-            memReq->dest = dest_addr;
-            memReq->size = 64;
-            memReq->time = curTick;
-            dcacheInterface->access(memReq);
-        }
-    }
-    else
-        assert(!fault->isAlignmentFault());
-
-    return fault;
-#else
-    panic("copy not implemented");
-    return NoFault;
-#endif
-}
-
 #if FULL_SYSTEM
 Addr
 BaseSimpleCPU::dbg_vtophys(Addr addr)
diff --git a/src/cpu/simple/base.hh b/src/cpu/simple/base.hh
index a713533fc..ed5d0b1a6 100644
--- a/src/cpu/simple/base.hh
+++ b/src/cpu/simple/base.hh
@@ -230,13 +230,6 @@ class BaseSimpleCPU : public BaseCPU
     Addr getEA()        { panic("BaseSimpleCPU::getEA() not implemented\n");
         M5_DUMMY_RETURN}
 
-    void prefetch(Addr addr, unsigned flags);
-    void writeHint(Addr addr, int size, unsigned flags);
-
-    Fault copySrcTranslate(Addr src);
-
-    Fault copy(Addr dest);
-
     // The register accessor methods provide the index of the
     // instruction's operand (e.g., 0 or 1), not the architectural
     // register index, to simplify the implementation of register
diff --git a/src/cpu/simple/timing.cc b/src/cpu/simple/timing.cc
index 863c28be2..2abe9cd59 100644
--- a/src/cpu/simple/timing.cc
+++ b/src/cpu/simple/timing.cc
@@ -1,4 +1,16 @@
 /*
+ * Copyright (c) 2010 ARM Limited
+ * All rights reserved
+ *
+ * The license below extends only to copyright in the software and shall
+ * not be construed as granting a license to any other intellectual
+ * property including but not limited to intellectual property relating
+ * to a hardware implementation of the functionality of the software
+ * licensed hereunder.  You may use the software subject to the license
+ * terms below provided that you ensure that this notice is replicated
+ * unmodified and in its entirety in all distributions of the software,
+ * modified or unmodified, in source code or in binary form.
+ *
  * Copyright (c) 2002-2005 The Regents of The University of Michigan
  * All rights reserved.
  *
@@ -789,8 +801,7 @@ TimingSimpleCPU::completeIfetch(PacketPtr pkt)
     }
 
     preExecute();
-    if (curStaticInst &&
-            curStaticInst->isMemRef() && !curStaticInst->isDataPrefetch()) {
+    if (curStaticInst && curStaticInst->isMemRef()) {
         // load or store: just send to dcache
         Fault fault = curStaticInst->initiateAcc(this, traceData);
         if (_status != Running) {