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-rw-r--r--src/cpu/simple/timing.cc6
1 files changed, 5 insertions, 1 deletions
diff --git a/src/cpu/simple/timing.cc b/src/cpu/simple/timing.cc
index 744bf8397..9253d8005 100644
--- a/src/cpu/simple/timing.cc
+++ b/src/cpu/simple/timing.cc
@@ -646,7 +646,6 @@ TimingSimpleCPU::completeIfetch(PacketPtr pkt)
// received a response from the icache: execute the received
// instruction
-
assert(!pkt || !pkt->isError());
assert(_status == IcacheWaitResponse);
@@ -655,6 +654,10 @@ TimingSimpleCPU::completeIfetch(PacketPtr pkt)
numCycles += curCycle() - previousCycle;
previousCycle = curCycle();
+ if (pkt)
+ pkt->req->setAccessLatency();
+
+
preExecute();
if (curStaticInst && curStaticInst->isMemRef()) {
// load or store: just send to dcache
@@ -749,6 +752,7 @@ TimingSimpleCPU::completeDataAccess(PacketPtr pkt)
assert(_status == DcacheWaitResponse || _status == DTBWaitResponse ||
pkt->req->getFlags().isSet(Request::NO_ACCESS));
+ pkt->req->setAccessLatency();
numCycles += curCycle() - previousCycle;
previousCycle = curCycle();