diff options
Diffstat (limited to 'src/cpu/simple')
| -rw-r--r-- | src/cpu/simple/atomic.cc | 8 | ||||
| -rw-r--r-- | src/cpu/simple/timing.cc | 4 |
2 files changed, 4 insertions, 8 deletions
diff --git a/src/cpu/simple/atomic.cc b/src/cpu/simple/atomic.cc index 1dd9675f9..ffd1c4d43 100644 --- a/src/cpu/simple/atomic.cc +++ b/src/cpu/simple/atomic.cc @@ -287,14 +287,12 @@ AtomicSimpleCPU::readMem(Addr addr, uint8_t * data, traceData->setAddr(addr); } - //The block size of our peer. - unsigned blockSize = dcachePort.peerBlockSize(); //The size of the data we're trying to read. int fullSize = size; //The address of the second part of this access if it needs to be split //across a cache line boundary. - Addr secondAddr = roundDown(addr + size - 1, blockSize); + Addr secondAddr = roundDown(addr + size - 1, cacheLineSize()); if (secondAddr > addr) size = secondAddr - addr; @@ -375,14 +373,12 @@ AtomicSimpleCPU::writeMem(uint8_t *data, unsigned size, traceData->setAddr(addr); } - //The block size of our peer. - unsigned blockSize = dcachePort.peerBlockSize(); //The size of the data we're trying to read. int fullSize = size; //The address of the second part of this access if it needs to be split //across a cache line boundary. - Addr secondAddr = roundDown(addr + size - 1, blockSize); + Addr secondAddr = roundDown(addr + size - 1, cacheLineSize()); if(secondAddr > addr) size = secondAddr - addr; diff --git a/src/cpu/simple/timing.cc b/src/cpu/simple/timing.cc index 1f453ca63..87a5245b2 100644 --- a/src/cpu/simple/timing.cc +++ b/src/cpu/simple/timing.cc @@ -404,7 +404,7 @@ TimingSimpleCPU::readMem(Addr addr, uint8_t *data, const int asid = 0; const ThreadID tid = 0; const Addr pc = thread->instAddr(); - unsigned block_size = dcachePort.peerBlockSize(); + unsigned block_size = cacheLineSize(); BaseTLB::Mode mode = BaseTLB::Read; if (traceData) { @@ -473,7 +473,7 @@ TimingSimpleCPU::writeMem(uint8_t *data, unsigned size, const int asid = 0; const ThreadID tid = 0; const Addr pc = thread->instAddr(); - unsigned block_size = dcachePort.peerBlockSize(); + unsigned block_size = cacheLineSize(); BaseTLB::Mode mode = BaseTLB::Write; if (traceData) { |