4 files changed, 12 insertions, 9 deletions

diff --git a/src/cpu/simple/atomic.cc b/src/cpu/simple/atomic.cc
index 045b80c80..2ec56c0f2 100644
--- a/src/cpu/simple/atomic.cc
+++ b/src/cpu/simple/atomic.cc
@@ -80,7 +80,8 @@ AtomicSimpleCPU::init()
 {
     BaseCPU::init();
 #if FULL_SYSTEM
-    for (int i = 0; i < threadContexts.size(); ++i) {
+    ThreadID size = threadContexts.size();
+    for (ThreadID i = 0; i < size; ++i) {
         ThreadContext *tc = threadContexts[i];
 
         // initialize CPU, including PC
@@ -227,7 +228,8 @@ AtomicSimpleCPU::takeOverFrom(BaseCPU *oldCPU)
 
     // if any of this CPU's ThreadContexts are active, mark the CPU as
     // running and schedule its tick event.
-    for (int i = 0; i < threadContexts.size(); ++i) {
+    ThreadID size = threadContexts.size();
+    for (ThreadID i = 0; i < size; ++i) {
         ThreadContext *tc = threadContexts[i];
         if (tc->status() == ThreadContext::Active && _status != Running) {
             _status = Running;
diff --git a/src/cpu/simple/base.cc b/src/cpu/simple/base.cc
index 5988f0e7e..61d034f31 100644
--- a/src/cpu/simple/base.cc
+++ b/src/cpu/simple/base.cc
@@ -200,7 +200,7 @@ BaseSimpleCPU::unserialize(Checkpoint *cp, const string &section)
 }
 
 void
-change_thread_state(int thread_number, int activate, int priority)
+change_thread_state(ThreadID tid, int activate, int priority)
 {
 }
 
diff --git a/src/cpu/simple/base.hh b/src/cpu/simple/base.hh
index e80606388..4e71d677e 100644
--- a/src/cpu/simple/base.hh
+++ b/src/cpu/simple/base.hh
@@ -399,13 +399,14 @@ class BaseSimpleCPU : public BaseCPU
         thread->setStCondFailures(sc_failures);
     }
 
-     MiscReg readRegOtherThread(int regIdx, int tid = -1)
+     MiscReg readRegOtherThread(int regIdx, ThreadID tid = InvalidThreadID)
      {
         panic("Simple CPU models do not support multithreaded "
               "register access.\n");
      }
 
-     void setRegOtherThread(int regIdx, const MiscReg &val, int tid = -1)
+     void setRegOtherThread(int regIdx, const MiscReg &val,
+                            ThreadID tid = InvalidThreadID)
      {
         panic("Simple CPU models do not support multithreaded "
               "register access.\n");
diff --git a/src/cpu/simple/timing.cc b/src/cpu/simple/timing.cc
index 590ba6b2d..6666f6f9d 100644
--- a/src/cpu/simple/timing.cc
+++ b/src/cpu/simple/timing.cc
@@ -437,13 +437,13 @@ TimingSimpleCPU::read(Addr addr, T &data, unsigned flags)
 {
     Fault fault;
     const int asid = 0;
-    const int thread_id = 0;
+    const ThreadID tid = 0;
     const Addr pc = thread->readPC();
     int block_size = dcachePort.peerBlockSize();
     int data_size = sizeof(T);
 
     RequestPtr req  = new Request(asid, addr, data_size,
-                                  flags, pc, _cpuId, thread_id);
+                                  flags, pc, _cpuId, tid);
 
     Addr split_addr = roundDown(addr + data_size - 1, block_size);
     assert(split_addr <= addr || split_addr - addr < block_size);
@@ -555,13 +555,13 @@ Fault
 TimingSimpleCPU::write(T data, Addr addr, unsigned flags, uint64_t *res)
 {
     const int asid = 0;
-    const int thread_id = 0;
+    const ThreadID tid = 0;
     const Addr pc = thread->readPC();
     int block_size = dcachePort.peerBlockSize();
     int data_size = sizeof(T);
 
     RequestPtr req = new Request(asid, addr, data_size,
-                                 flags, pc, _cpuId, thread_id);
+                                 flags, pc, _cpuId, tid);
 
     Addr split_addr = roundDown(addr + data_size - 1, block_size);
     assert(split_addr <= addr || split_addr - addr < block_size);