5 files changed, 131 insertions, 41 deletions
diff --git a/src/cpu/simple/atomic.cc b/src/cpu/simple/atomic.cc
index 12bfdeb9b..c396f5033 100644
--- a/src/cpu/simple/atomic.cc
+++ b/src/cpu/simple/atomic.cc
@@ -33,6 +33,7 @@
 #include "cpu/simple/atomic.hh"
 #include "mem/packet_impl.hh"
 #include "sim/builder.hh"
+#include "sim/system.hh"
 
 using namespace std;
 using namespace TheISA;
@@ -158,18 +159,31 @@ AtomicSimpleCPU::~AtomicSimpleCPU()
 void
 AtomicSimpleCPU::serialize(ostream &os)
 {
-    SERIALIZE_ENUM(_status);
-    BaseSimpleCPU::serialize(os);
+    SimObject::State so_state = SimObject::getState();
+    SERIALIZE_ENUM(so_state);
     nameOut(os, csprintf("%s.tickEvent", name()));
     tickEvent.serialize(os);
+    BaseSimpleCPU::serialize(os);
 }
 
 void
 AtomicSimpleCPU::unserialize(Checkpoint *cp, const string &section)
 {
-    UNSERIALIZE_ENUM(_status);
-    BaseSimpleCPU::unserialize(cp, section);
+    SimObject::State so_state;
+    UNSERIALIZE_ENUM(so_state);
     tickEvent.unserialize(cp, csprintf("%s.tickEvent", section));
+    BaseSimpleCPU::unserialize(cp, section);
+}
+
+void
+AtomicSimpleCPU::resume()
+{
+    assert(system->getMemoryMode() == System::Atomic);
+    changeState(SimObject::Running);
+    if (thread->status() == ThreadContext::Active) {
+        if (!tickEvent.scheduled())
+            tickEvent.schedule(curTick);
+    }
 }
 
 void
@@ -451,11 +465,11 @@ BEGIN_DECLARE_SIM_OBJECT_PARAMS(AtomicSimpleCPU)
     Param<Counter> max_loads_any_thread;
     Param<Counter> max_loads_all_threads;
     SimObjectParam<MemObject *> mem;
+    SimObjectParam<System *> system;
 
 #if FULL_SYSTEM
     SimObjectParam<AlphaITB *> itb;
     SimObjectParam<AlphaDTB *> dtb;
-    SimObjectParam<System *> system;
     Param<int> cpu_id;
     Param<Tick> profile;
 #else
@@ -483,11 +497,11 @@ BEGIN_INIT_SIM_OBJECT_PARAMS(AtomicSimpleCPU)
     INIT_PARAM(max_loads_all_threads,
                "terminate when all threads have reached this load count"),
     INIT_PARAM(mem, "memory"),
+    INIT_PARAM(system, "system object"),
 
 #if FULL_SYSTEM
     INIT_PARAM(itb, "Instruction TLB"),
     INIT_PARAM(dtb, "Data TLB"),
-    INIT_PARAM(system, "system object"),
     INIT_PARAM(cpu_id, "processor ID"),
     INIT_PARAM(profile, ""),
 #else
@@ -520,11 +534,11 @@ CREATE_SIM_OBJECT(AtomicSimpleCPU)
     params->width = width;
     params->simulate_stalls = simulate_stalls;
     params->mem = mem;
+    params->system = system;
 
 #if FULL_SYSTEM
     params->itb = itb;
     params->dtb = dtb;
-    params->system = system;
     params->cpu_id = cpu_id;
     params->profile = profile;
 #else
diff --git a/src/cpu/simple/atomic.hh b/src/cpu/simple/atomic.hh
index 179b4a721..b602af558 100644
--- a/src/cpu/simple/atomic.hh
+++ b/src/cpu/simple/atomic.hh
@@ -126,6 +126,7 @@ class AtomicSimpleCPU : public BaseSimpleCPU
 
     virtual void serialize(std::ostream &os);
     virtual void unserialize(Checkpoint *cp, const std::string &section);
+    virtual void resume();
 
     void switchOut();
     void takeOverFrom(BaseCPU *oldCPU);
diff --git a/src/cpu/simple/base.cc b/src/cpu/simple/base.cc
index a50541189..801c96c88 100644
--- a/src/cpu/simple/base.cc
+++ b/src/cpu/simple/base.cc
@@ -26,10 +26,10 @@
  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  *
  * Authors: Steve Reinhardt
- *          Korey Sewell
  */
 
 #include "arch/utility.hh"
+#include "arch/faults.hh"
 #include "base/cprintf.hh"
 #include "base/inifile.hh"
 #include "base/loader/symtab.hh"
@@ -55,10 +55,10 @@
 #include "sim/sim_events.hh"
 #include "sim/sim_object.hh"
 #include "sim/stats.hh"
+#include "sim/system.hh"
 
 #if FULL_SYSTEM
 #include "base/remote_gdb.hh"
-#include "sim/system.hh"
 #include "arch/tlb.hh"
 #include "arch/stacktrace.hh"
 #include "arch/vtophys.hh"
@@ -178,8 +178,8 @@ void
 BaseSimpleCPU::serialize(ostream &os)
 {
     BaseCPU::serialize(os);
-    SERIALIZE_SCALAR(inst);
-    nameOut(os, csprintf("%s.xc", name()));
+//    SERIALIZE_SCALAR(inst);
+    nameOut(os, csprintf("%s.xc.0", name()));
     thread->serialize(os);
 }
 
@@ -187,8 +187,8 @@ void
 BaseSimpleCPU::unserialize(Checkpoint *cp, const string &section)
 {
     BaseCPU::unserialize(cp, section);
-    UNSERIALIZE_SCALAR(inst);
-    thread->unserialize(cp, csprintf("%s.xc", section));
+//    UNSERIALIZE_SCALAR(inst);
+    thread->unserialize(cp, csprintf("%s.xc.0", section));
 }
 
 void
@@ -455,6 +455,7 @@ BaseSimpleCPU::advancePC(Fault fault)
 #else
         thread->setNextPC(thread->readNextNPC());
         thread->setNextNPC(thread->readNextNPC() + sizeof(MachInst));
+        assert(thread->readNextPC() != thread->readNextNPC());
 #endif
 
     }
diff --git a/src/cpu/simple/timing.cc b/src/cpu/simple/timing.cc
index e55301c6b..5c1654f7e 100644
--- a/src/cpu/simple/timing.cc
+++ b/src/cpu/simple/timing.cc
@@ -33,6 +33,7 @@
 #include "cpu/simple/timing.hh"
 #include "mem/packet_impl.hh"
 #include "sim/builder.hh"
+#include "sim/system.hh"
 
 using namespace std;
 using namespace TheISA;
@@ -84,14 +85,22 @@ TimingSimpleCPU::CpuPort::recvStatusChange(Status status)
     panic("TimingSimpleCPU doesn't expect recvStatusChange callback!");
 }
 
+
+void
+TimingSimpleCPU::CpuPort::TickEvent::schedule(Packet *_pkt, Tick t)
+{
+    pkt = _pkt;
+    Event::schedule(t);
+}
+
 TimingSimpleCPU::TimingSimpleCPU(Params *p)
-    : BaseSimpleCPU(p), icachePort(this), dcachePort(this)
+    : BaseSimpleCPU(p), icachePort(this, p->clock), dcachePort(this, p->clock)
 {
     _status = Idle;
     ifetch_pkt = dcache_pkt = NULL;
     drainEvent = NULL;
     fetchEvent = NULL;
-    state = SimObject::Timing;
+    changeState(SimObject::Running);
 }
 
 
@@ -102,29 +111,31 @@ TimingSimpleCPU::~TimingSimpleCPU()
 void
 TimingSimpleCPU::serialize(ostream &os)
 {
-    SERIALIZE_ENUM(_status);
+    SimObject::State so_state = SimObject::getState();
+    SERIALIZE_ENUM(so_state);
     BaseSimpleCPU::serialize(os);
 }
 
 void
 TimingSimpleCPU::unserialize(Checkpoint *cp, const string &section)
 {
-    UNSERIALIZE_ENUM(_status);
+    SimObject::State so_state;
+    UNSERIALIZE_ENUM(so_state);
     BaseSimpleCPU::unserialize(cp, section);
 }
 
-bool
+unsigned int
 TimingSimpleCPU::drain(Event *drain_event)
 {
     // TimingSimpleCPU is ready to drain if it's not waiting for
     // an access to complete.
     if (status() == Idle || status() == Running || status() == SwitchedOut) {
-        changeState(SimObject::DrainedTiming);
-        return true;
+        changeState(SimObject::Drained);
+        return 0;
     } else {
         changeState(SimObject::Draining);
         drainEvent = drain_event;
-        return false;
+        return 1;
     }
 }
 
@@ -134,7 +145,9 @@ TimingSimpleCPU::resume()
     if (_status != SwitchedOut && _status != Idle) {
         // Delete the old event if it existed.
         if (fetchEvent) {
-            assert(!fetchEvent->scheduled());
+            if (fetchEvent->scheduled())
+                fetchEvent->deschedule();
+
             delete fetchEvent;
         }
 
@@ -142,12 +155,9 @@ TimingSimpleCPU::resume()
             new EventWrapper<TimingSimpleCPU, &TimingSimpleCPU::fetch>(this, false);
         fetchEvent->schedule(curTick);
     }
-}
 
-void
-TimingSimpleCPU::setMemoryMode(State new_mode)
-{
-    assert(new_mode == SimObject::Timing);
+    assert(system->getMemoryMode() == System::Timing);
+    changeState(SimObject::Running);
 }
 
 void
@@ -460,11 +470,26 @@ TimingSimpleCPU::completeIfetch(Packet *pkt)
     }
 }
 
+void
+TimingSimpleCPU::IcachePort::ITickEvent::process()
+{
+    cpu->completeIfetch(pkt);
+}
 
 bool
 TimingSimpleCPU::IcachePort::recvTiming(Packet *pkt)
 {
-    cpu->completeIfetch(pkt);
+    // These next few lines could be replaced with something faster
+    // who knows what though
+    Tick time = pkt->req->getTime();
+    while (time < curTick)
+        time += lat;
+
+    if (time == curTick)
+        cpu->completeIfetch(pkt);
+    else
+        tickEvent.schedule(pkt, time);
+
     return true;
 }
 
@@ -514,18 +539,32 @@ void
 TimingSimpleCPU::completeDrain()
 {
     DPRINTF(Config, "Done draining\n");
-    changeState(SimObject::DrainedTiming);
+    changeState(SimObject::Drained);
     drainEvent->process();
 }
 
 bool
 TimingSimpleCPU::DcachePort::recvTiming(Packet *pkt)
 {
-    cpu->completeDataAccess(pkt);
+    Tick time = pkt->req->getTime();
+    while (time < curTick)
+        time += lat;
+
+    if (time == curTick)
+        cpu->completeDataAccess(pkt);
+    else
+        tickEvent.schedule(pkt, time);
+
     return true;
 }
 
 void
+TimingSimpleCPU::DcachePort::DTickEvent::process()
+{
+    cpu->completeDataAccess(pkt);
+}
+
+void
 TimingSimpleCPU::DcachePort::recvRetry()
 {
     // we shouldn't get a retry unless we have a packet that we're
@@ -551,11 +590,11 @@ BEGIN_DECLARE_SIM_OBJECT_PARAMS(TimingSimpleCPU)
     Param<Counter> max_loads_any_thread;
     Param<Counter> max_loads_all_threads;
     SimObjectParam<MemObject *> mem;
+    SimObjectParam<System *> system;
 
 #if FULL_SYSTEM
     SimObjectParam<AlphaITB *> itb;
     SimObjectParam<AlphaDTB *> dtb;
-    SimObjectParam<System *> system;
     Param<int> cpu_id;
     Param<Tick> profile;
 #else
@@ -583,11 +622,11 @@ BEGIN_INIT_SIM_OBJECT_PARAMS(TimingSimpleCPU)
     INIT_PARAM(max_loads_all_threads,
                "terminate when all threads have reached this load count"),
     INIT_PARAM(mem, "memory"),
+    INIT_PARAM(system, "system object"),
 
 #if FULL_SYSTEM
     INIT_PARAM(itb, "Instruction TLB"),
     INIT_PARAM(dtb, "Data TLB"),
-    INIT_PARAM(system, "system object"),
     INIT_PARAM(cpu_id, "processor ID"),
     INIT_PARAM(profile, ""),
 #else
@@ -618,11 +657,11 @@ CREATE_SIM_OBJECT(TimingSimpleCPU)
     params->functionTrace = function_trace;
     params->functionTraceStart = function_trace_start;
     params->mem = mem;
+    params->system = system;
 
 #if FULL_SYSTEM
     params->itb = itb;
     params->dtb = dtb;
-    params->system = system;
     params->cpu_id = cpu_id;
     params->profile = profile;
 #else
diff --git a/src/cpu/simple/timing.hh b/src/cpu/simple/timing.hh
index 0a3f91e6c..d03fa4bc0 100644
--- a/src/cpu/simple/timing.hh
+++ b/src/cpu/simple/timing.hh
@@ -74,11 +74,12 @@ class TimingSimpleCPU : public BaseSimpleCPU
     {
       protected:
         TimingSimpleCPU *cpu;
+        Tick lat;
 
       public:
 
-        CpuPort(const std::string &_name, TimingSimpleCPU *_cpu)
-            : Port(_name), cpu(_cpu)
+        CpuPort(const std::string &_name, TimingSimpleCPU *_cpu, Tick _lat)
+            : Port(_name), cpu(_cpu), lat(_lat)
         { }
 
       protected:
@@ -92,14 +93,26 @@ class TimingSimpleCPU : public BaseSimpleCPU
         virtual void getDeviceAddressRanges(AddrRangeList &resp,
             AddrRangeList &snoop)
         { resp.clear(); snoop.clear(); }
+
+        struct TickEvent : public Event
+        {
+            Packet *pkt;
+            TimingSimpleCPU *cpu;
+
+            TickEvent(TimingSimpleCPU *_cpu)
+                :Event(&mainEventQueue), cpu(_cpu) {}
+            const char *description() { return "Timing CPU clock event"; }
+            void schedule(Packet *_pkt, Tick t);
+        };
+
     };
 
     class IcachePort : public CpuPort
     {
       public:
 
-        IcachePort(TimingSimpleCPU *_cpu)
-            : CpuPort(_cpu->name() + "-iport", _cpu)
+        IcachePort(TimingSimpleCPU *_cpu, Tick _lat)
+            : CpuPort(_cpu->name() + "-iport", _cpu, _lat), tickEvent(_cpu)
         { }
 
       protected:
@@ -107,14 +120,26 @@ class TimingSimpleCPU : public BaseSimpleCPU
         virtual bool recvTiming(Packet *pkt);
 
         virtual void recvRetry();
+
+        struct ITickEvent : public TickEvent
+        {
+
+            ITickEvent(TimingSimpleCPU *_cpu)
+                : TickEvent(_cpu) {}
+            void process();
+            const char *description() { return "Timing CPU clock event"; }
+        };
+
+        ITickEvent tickEvent;
+
     };
 
     class DcachePort : public CpuPort
     {
       public:
 
-        DcachePort(TimingSimpleCPU *_cpu)
-            : CpuPort(_cpu->name() + "-dport", _cpu)
+        DcachePort(TimingSimpleCPU *_cpu, Tick _lat)
+            : CpuPort(_cpu->name() + "-dport", _cpu, _lat), tickEvent(_cpu)
         { }
 
       protected:
@@ -122,6 +147,17 @@ class TimingSimpleCPU : public BaseSimpleCPU
         virtual bool recvTiming(Packet *pkt);
 
         virtual void recvRetry();
+
+        struct DTickEvent : public TickEvent
+        {
+            DTickEvent(TimingSimpleCPU *_cpu)
+                : TickEvent(_cpu) {}
+            void process();
+            const char *description() { return "Timing CPU clock event"; }
+        };
+
+        DTickEvent tickEvent;
+
     };
 
     IcachePort icachePort;
@@ -137,9 +173,8 @@ class TimingSimpleCPU : public BaseSimpleCPU
     virtual void serialize(std::ostream &os);
     virtual void unserialize(Checkpoint *cp, const std::string &section);
 
-    virtual bool drain(Event *drain_event);
+    virtual unsigned int drain(Event *drain_event);
     virtual void resume();
-    virtual void setMemoryMode(State new_mode);
 
     void switchOut();
     void takeOverFrom(BaseCPU *oldCPU);