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-rw-r--r--src/cpu/simple/atomic.cc30
-rw-r--r--src/cpu/simple/base.cc39
-rw-r--r--src/cpu/simple/base.hh34
-rw-r--r--src/cpu/simple/timing.cc28
4 files changed, 51 insertions, 80 deletions
diff --git a/src/cpu/simple/atomic.cc b/src/cpu/simple/atomic.cc
index 5376519d4..fed94ffd8 100644
--- a/src/cpu/simple/atomic.cc
+++ b/src/cpu/simple/atomic.cc
@@ -42,6 +42,7 @@
#include "params/AtomicSimpleCPU.hh"
#include "sim/faults.hh"
#include "sim/system.hh"
+#include "sim/full_system.hh"
using namespace std;
using namespace TheISA;
@@ -83,15 +84,14 @@ void
AtomicSimpleCPU::init()
{
BaseCPU::init();
-#if FULL_SYSTEM
- ThreadID size = threadContexts.size();
- for (ThreadID i = 0; i < size; ++i) {
- ThreadContext *tc = threadContexts[i];
-
- // initialize CPU, including PC
- TheISA::initCPU(tc, tc->contextId());
+ if (FullSystem) {
+ ThreadID size = threadContexts.size();
+ for (ThreadID i = 0; i < size; ++i) {
+ ThreadContext *tc = threadContexts[i];
+ // initialize CPU, including PC
+ TheISA::initCPU(tc, tc->contextId());
+ }
}
-#endif
if (hasPhysMemPort) {
bool snoop = false;
AddrRangeList pmAddrList;
@@ -150,11 +150,11 @@ AtomicSimpleCPU::DcachePort::setPeer(Port *port)
{
Port::setPeer(port);
-#if FULL_SYSTEM
- // Update the ThreadContext's memory ports (Functional/Virtual
- // Ports)
- cpu->tcBase()->connectMemPorts(cpu->tcBase());
-#endif
+ if (FullSystem) {
+ // Update the ThreadContext's memory ports (Functional/Virtual
+ // Ports)
+ cpu->tcBase()->connectMemPorts(cpu->tcBase());
+ }
}
AtomicSimpleCPU::AtomicSimpleCPU(AtomicSimpleCPUParams *p)
@@ -616,9 +616,7 @@ AtomicSimpleCPU *
AtomicSimpleCPUParams::create()
{
numThreads = 1;
-#if !FULL_SYSTEM
- if (workload.size() != 1)
+ if (!FullSystem && workload.size() != 1)
panic("only one workload allowed");
-#endif
return new AtomicSimpleCPU(this);
}
diff --git a/src/cpu/simple/base.cc b/src/cpu/simple/base.cc
index 70e2c39e6..610cc6b89 100644
--- a/src/cpu/simple/base.cc
+++ b/src/cpu/simple/base.cc
@@ -41,7 +41,11 @@
*/
#include "arch/faults.hh"
+#include "arch/kernel_stats.hh"
+#include "arch/stacktrace.hh"
+#include "arch/tlb.hh"
#include "arch/utility.hh"
+#include "arch/vtophys.hh"
#include "base/loader/symtab.hh"
#include "base/cp_annotate.hh"
#include "base/cprintf.hh"
@@ -63,37 +67,29 @@
#include "debug/Decode.hh"
#include "debug/Fetch.hh"
#include "debug/Quiesce.hh"
+#include "mem/mem_object.hh"
#include "mem/packet.hh"
#include "mem/request.hh"
#include "params/BaseSimpleCPU.hh"
#include "sim/byteswap.hh"
#include "sim/debug.hh"
+#include "sim/full_system.hh"
#include "sim/sim_events.hh"
#include "sim/sim_object.hh"
#include "sim/stats.hh"
#include "sim/system.hh"
-#if FULL_SYSTEM
-#include "arch/kernel_stats.hh"
-#include "arch/stacktrace.hh"
-#include "arch/tlb.hh"
-#include "arch/vtophys.hh"
-#else // !FULL_SYSTEM
-#include "mem/mem_object.hh"
-#endif // FULL_SYSTEM
-
using namespace std;
using namespace TheISA;
BaseSimpleCPU::BaseSimpleCPU(BaseSimpleCPUParams *p)
: BaseCPU(p), traceData(NULL), thread(NULL), predecoder(NULL)
{
-#if FULL_SYSTEM
- thread = new SimpleThread(this, 0, p->system, p->itb, p->dtb);
-#else
- thread = new SimpleThread(this, /* thread_num */ 0, p->workload[0],
- p->itb, p->dtb);
-#endif // !FULL_SYSTEM
+ if (FullSystem)
+ thread = new SimpleThread(this, 0, p->system, p->itb, p->dtb);
+ else
+ thread = new SimpleThread(this, /* thread_num */ 0, p->workload[0],
+ p->itb, p->dtb);
thread->setStatus(ThreadContext::Halted);
@@ -290,15 +286,12 @@ change_thread_state(ThreadID tid, int activate, int priority)
{
}
-#if FULL_SYSTEM
Addr
BaseSimpleCPU::dbg_vtophys(Addr addr)
{
return vtophys(tc, addr);
}
-#endif // FULL_SYSTEM
-#if FULL_SYSTEM
void
BaseSimpleCPU::wakeup()
{
@@ -308,12 +301,10 @@ BaseSimpleCPU::wakeup()
DPRINTF(Quiesce,"Suspended Processor awoke\n");
thread->activate();
}
-#endif // FULL_SYSTEM
void
BaseSimpleCPU::checkForInterrupts()
{
-#if FULL_SYSTEM
if (checkInterrupts(tc)) {
Fault interrupt = interrupts->getInterrupt(tc);
@@ -324,7 +315,6 @@ BaseSimpleCPU::checkForInterrupts()
predecoder.reset();
}
}
-#endif
}
@@ -422,15 +412,13 @@ BaseSimpleCPU::postExecute()
TheISA::PCState pc = tc->pcState();
Addr instAddr = pc.instAddr();
-#if FULL_SYSTEM
- if (thread->profile) {
+ if (FullSystem && thread->profile) {
bool usermode = TheISA::inUserMode(tc);
thread->profilePC = usermode ? 1 : instAddr;
ProfileNode *node = thread->profile->consume(tc, curStaticInst);
if (node)
thread->profileNode = node;
}
-#endif
if (curStaticInst->isMemRef()) {
numMemRefs++;
@@ -478,7 +466,8 @@ BaseSimpleCPU::postExecute()
}
/* End power model statistics */
- traceFunctions(instAddr);
+ if (FullSystem)
+ traceFunctions(instAddr);
if (traceData) {
traceData->dump();
diff --git a/src/cpu/simple/base.hh b/src/cpu/simple/base.hh
index ad281aa2b..6272560a1 100644
--- a/src/cpu/simple/base.hh
+++ b/src/cpu/simple/base.hh
@@ -35,7 +35,6 @@
#include "arch/predecoder.hh"
#include "base/statistics.hh"
-#include "config/full_system.hh"
#include "config/the_isa.hh"
#include "cpu/base.hh"
#include "cpu/decode.hh"
@@ -46,30 +45,22 @@
#include "mem/port.hh"
#include "mem/request.hh"
#include "sim/eventq.hh"
+#include "sim/full_system.hh"
#include "sim/system.hh"
// forward declarations
-#if FULL_SYSTEM
-class Processor;
-namespace TheISA
-{
- class ITB;
- class DTB;
-}
+class Checkpoint;
class MemObject;
-
-#else
-
class Process;
-
-#endif // FULL_SYSTEM
+class Processor;
+class ThreadContext;
namespace TheISA
{
+ class DTB;
+ class ITB;
class Predecoder;
}
-class ThreadContext;
-class Checkpoint;
namespace Trace {
class InstRecord;
@@ -141,11 +132,9 @@ class BaseSimpleCPU : public BaseCPU
public:
-#if FULL_SYSTEM
Addr dbg_vtophys(Addr addr);
bool interval_stats;
-#endif
// current instruction
TheISA::MachInst inst;
@@ -399,19 +388,16 @@ class BaseSimpleCPU : public BaseCPU
//Fault CacheOp(uint8_t Op, Addr EA);
-#if FULL_SYSTEM
Fault hwrei() { return thread->hwrei(); }
bool simPalCheck(int palFunc) { return thread->simPalCheck(palFunc); }
-#endif
void
syscall(int64_t callnum)
{
-#if FULL_SYSTEM
- panic("Syscall emulation isn't available in FS mode.\n");
-#else
- thread->syscall(callnum);
-#endif
+ if (FullSystem)
+ panic("Syscall emulation isn't available in FS mode.\n");
+ else
+ thread->syscall(callnum);
}
bool misspeculating() { return thread->misspeculating(); }
diff --git a/src/cpu/simple/timing.cc b/src/cpu/simple/timing.cc
index e2151d974..983672c27 100644
--- a/src/cpu/simple/timing.cc
+++ b/src/cpu/simple/timing.cc
@@ -54,6 +54,7 @@
#include "mem/packet_access.hh"
#include "params/TimingSimpleCPU.hh"
#include "sim/faults.hh"
+#include "sim/full_system.hh"
#include "sim/system.hh"
using namespace std;
@@ -74,14 +75,13 @@ void
TimingSimpleCPU::init()
{
BaseCPU::init();
-#if FULL_SYSTEM
- for (int i = 0; i < threadContexts.size(); ++i) {
- ThreadContext *tc = threadContexts[i];
-
- // initialize CPU, including PC
- TheISA::initCPU(tc, _cpuId);
+ if (FullSystem) {
+ for (int i = 0; i < threadContexts.size(); ++i) {
+ ThreadContext *tc = threadContexts[i];
+ // initialize CPU, including PC
+ TheISA::initCPU(tc, _cpuId);
+ }
}
-#endif
}
Tick
@@ -879,11 +879,11 @@ TimingSimpleCPU::DcachePort::setPeer(Port *port)
{
Port::setPeer(port);
-#if FULL_SYSTEM
- // Update the ThreadContext's memory ports (Functional/Virtual
- // Ports)
- cpu->tcBase()->connectMemPorts(cpu->tcBase());
-#endif
+ if (FullSystem) {
+ // Update the ThreadContext's memory ports (Functional/Virtual
+ // Ports)
+ cpu->tcBase()->connectMemPorts(cpu->tcBase());
+ }
}
bool
@@ -1007,9 +1007,7 @@ TimingSimpleCPU *
TimingSimpleCPUParams::create()
{
numThreads = 1;
-#if !FULL_SYSTEM
- if (workload.size() != 1)
+ if (!FullSystem && workload.size() != 1)
panic("only one workload allowed");
-#endif
return new TimingSimpleCPU(this);
}
generated by cgit v1.2.3 (git 2.25.1) at 2025-01-06 07:28:25 +0000