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-rw-r--r--src/cpu/simple/atomic.cc6
-rw-r--r--src/cpu/simple/timing.cc12
2 files changed, 9 insertions, 9 deletions
diff --git a/src/cpu/simple/atomic.cc b/src/cpu/simple/atomic.cc
index 3ce0ba172..045b0160f 100644
--- a/src/cpu/simple/atomic.cc
+++ b/src/cpu/simple/atomic.cc
@@ -322,7 +322,7 @@ AtomicSimpleCPU::read(Addr addr, T &data, unsigned flags)
// Now do the access.
if (fault == NoFault) {
Packet pkt = Packet(req,
- req->isLocked() ? MemCmd::LoadLockedReq : MemCmd::ReadReq,
+ req->isLlsc() ? MemCmd::LoadLockedReq : MemCmd::ReadReq,
Packet::Broadcast);
pkt.dataStatic(dataPtr);
@@ -338,7 +338,7 @@ AtomicSimpleCPU::read(Addr addr, T &data, unsigned flags)
assert(!pkt.isError());
- if (req->isLocked()) {
+ if (req->isLlsc()) {
TheISA::handleLockedRead(thread, req);
}
}
@@ -462,7 +462,7 @@ AtomicSimpleCPU::write(T data, Addr addr, unsigned flags, uint64_t *res)
MemCmd cmd = MemCmd::WriteReq; // default
bool do_access = true; // flag to suppress cache access
- if (req->isLocked()) {
+ if (req->isLlsc()) {
cmd = MemCmd::StoreCondReq;
do_access = TheISA::handleLockedWrite(thread, req);
} else if (req->isSwap()) {
diff --git a/src/cpu/simple/timing.cc b/src/cpu/simple/timing.cc
index 64c4108a7..905acb6d4 100644
--- a/src/cpu/simple/timing.cc
+++ b/src/cpu/simple/timing.cc
@@ -290,7 +290,7 @@ TimingSimpleCPU::sendData(Fault fault, RequestPtr req,
} else {
bool do_access = true; // flag to suppress cache access
- if (req->isLocked()) {
+ if (req->isLlsc()) {
do_access = TheISA::handleLockedWrite(thread, req);
} else if (req->isCondSwap()) {
assert(res);
@@ -384,11 +384,11 @@ TimingSimpleCPU::buildPacket(PacketPtr &pkt, RequestPtr req, bool read)
MemCmd cmd;
if (read) {
cmd = MemCmd::ReadReq;
- if (req->isLocked())
+ if (req->isLlsc())
cmd = MemCmd::LoadLockedReq;
} else {
cmd = MemCmd::WriteReq;
- if (req->isLocked()) {
+ if (req->isLlsc()) {
cmd = MemCmd::StoreCondReq;
} else if (req->isSwap()) {
cmd = MemCmd::SwapReq;
@@ -452,7 +452,7 @@ TimingSimpleCPU::read(Addr addr, T &data, unsigned flags)
_status = DTBWaitResponse;
if (split_addr > addr) {
RequestPtr req1, req2;
- assert(!req->isLocked() && !req->isSwap());
+ assert(!req->isLlsc() && !req->isSwap());
req->splitOnVaddr(split_addr, req1, req2);
typedef SplitDataTranslation::WholeTranslationState WholeState;
@@ -571,7 +571,7 @@ TimingSimpleCPU::write(T data, Addr addr, unsigned flags, uint64_t *res)
_status = DTBWaitResponse;
if (split_addr > addr) {
RequestPtr req1, req2;
- assert(!req->isLocked() && !req->isSwap());
+ assert(!req->isLlsc() && !req->isSwap());
req->splitOnVaddr(split_addr, req1, req2);
typedef SplitDataTranslation::WholeTranslationState WholeState;
@@ -904,7 +904,7 @@ TimingSimpleCPU::completeDataAccess(PacketPtr pkt)
// the locked flag may be cleared on the response packet, so check
// pkt->req and not pkt to see if it was a load-locked
- if (pkt->isRead() && pkt->req->isLocked()) {
+ if (pkt->isRead() && pkt->req->isLlsc()) {
TheISA::handleLockedRead(thread, pkt->req);
}