4 files changed, 26 insertions, 0 deletions
diff --git a/src/cpu/simple/atomic.cc b/src/cpu/simple/atomic.cc
index 4553c0ae2..aa548b46f 100644
--- a/src/cpu/simple/atomic.cc
+++ b/src/cpu/simple/atomic.cc
@@ -783,6 +783,13 @@ AtomicSimpleCPU::tick()
 }
 
 
+void
+AtomicSimpleCPU::printAddr(Addr a)
+{
+    dcachePort.printAddr(a);
+}
+
+
 ////////////////////////////////////////////////////////////////////////
 //
 //  AtomicSimpleCPU Simulation Object
diff --git a/src/cpu/simple/atomic.hh b/src/cpu/simple/atomic.hh
index f68f41a90..f14dd6f99 100644
--- a/src/cpu/simple/atomic.hh
+++ b/src/cpu/simple/atomic.hh
@@ -156,6 +156,12 @@ class AtomicSimpleCPU : public BaseSimpleCPU
             int size, unsigned flags);
     Fault translateDataWriteAddr(Addr vaddr, Addr &paddr,
             int size, unsigned flags);
+
+    /**
+     * Print state of address in memory system via PrintReq (for
+     * debugging).
+     */
+    void printAddr(Addr a);
 };
 
 #endif // __CPU_SIMPLE_ATOMIC_HH__
diff --git a/src/cpu/simple/timing.cc b/src/cpu/simple/timing.cc
index 2f3ee5c73..fc35f2666 100644
--- a/src/cpu/simple/timing.cc
+++ b/src/cpu/simple/timing.cc
@@ -822,6 +822,13 @@ TimingSimpleCPU::IprEvent::description()
 }
 
 
+void
+TimingSimpleCPU::printAddr(Addr a)
+{
+    dcachePort.printAddr(a);
+}
+
+
 ////////////////////////////////////////////////////////////////////////
 //
 //  TimingSimpleCPU Simulation Object
diff --git a/src/cpu/simple/timing.hh b/src/cpu/simple/timing.hh
index d7554f6de..79fbe0f5f 100644
--- a/src/cpu/simple/timing.hh
+++ b/src/cpu/simple/timing.hh
@@ -203,6 +203,12 @@ class TimingSimpleCPU : public BaseSimpleCPU
     void completeDataAccess(PacketPtr );
     void advanceInst(Fault fault);
 
+    /**
+     * Print state of address in memory system via PrintReq (for
+     * debugging).
+     */
+    void printAddr(Addr a);
+
   private:
 
     typedef EventWrapper<TimingSimpleCPU, &TimingSimpleCPU::fetch> FetchEvent;