diff options
Diffstat (limited to 'src/cpu/simple')
-rw-r--r-- | src/cpu/simple/atomic.hh | 2 | ||||
-rw-r--r-- | src/cpu/simple/timing.cc | 17 | ||||
-rw-r--r-- | src/cpu/simple/timing.hh | 5 |
3 files changed, 15 insertions, 9 deletions
diff --git a/src/cpu/simple/atomic.hh b/src/cpu/simple/atomic.hh index 3e6238f7d..e88c93cce 100644 --- a/src/cpu/simple/atomic.hh +++ b/src/cpu/simple/atomic.hh @@ -91,7 +91,7 @@ class AtomicSimpleCPU : public BaseSimpleCPU protected: - virtual Tick recvAtomic(PacketPtr pkt) + virtual Tick recvAtomicSnoop(PacketPtr pkt) { // Snooping a coherence request, just return return 0; diff --git a/src/cpu/simple/timing.cc b/src/cpu/simple/timing.cc index f661756da..d52003f19 100644 --- a/src/cpu/simple/timing.cc +++ b/src/cpu/simple/timing.cc @@ -1,5 +1,5 @@ /* - * Copyright (c) 2010 ARM Limited + * Copyright (c) 2010-2012 ARM Limited * All rights reserved * * The license below extends only to copyright in the software and shall @@ -718,7 +718,8 @@ TimingSimpleCPU::IcachePort::ITickEvent::process() bool TimingSimpleCPU::IcachePort::recvTiming(PacketPtr pkt) { - if (pkt->isResponse() && !pkt->wasNacked()) { + assert(pkt->isResponse()); + if (!pkt->wasNacked()) { DPRINTF(SimpleCPU, "Received timing response %#x\n", pkt->getAddr()); // delay processing of returned data until next CPU clock edge Tick next_tick = cpu->nextCycle(curTick()); @@ -729,7 +730,7 @@ TimingSimpleCPU::IcachePort::recvTiming(PacketPtr pkt) tickEvent.schedule(pkt, next_tick); return true; - } else if (pkt->wasNacked()) { + } else { assert(cpu->_status == IcacheWaitResponse); pkt->reinitNacked(); if (!sendTiming(pkt)) { @@ -737,7 +738,7 @@ TimingSimpleCPU::IcachePort::recvTiming(PacketPtr pkt) cpu->ifetch_pkt = pkt; } } - //Snooping a Coherence Request, do nothing + return true; } @@ -838,7 +839,8 @@ TimingSimpleCPU::completeDrain() bool TimingSimpleCPU::DcachePort::recvTiming(PacketPtr pkt) { - if (pkt->isResponse() && !pkt->wasNacked()) { + assert(pkt->isResponse()); + if (!pkt->wasNacked()) { // delay processing of returned data until next CPU clock edge Tick next_tick = cpu->nextCycle(curTick()); @@ -858,8 +860,7 @@ TimingSimpleCPU::DcachePort::recvTiming(PacketPtr pkt) } return true; - } - else if (pkt->wasNacked()) { + } else { assert(cpu->_status == DcacheWaitResponse); pkt->reinitNacked(); if (!sendTiming(pkt)) { @@ -867,7 +868,7 @@ TimingSimpleCPU::DcachePort::recvTiming(PacketPtr pkt) cpu->dcache_pkt = pkt; } } - //Snooping a Coherence Request, do nothing + return true; } diff --git a/src/cpu/simple/timing.hh b/src/cpu/simple/timing.hh index e0c5c89f7..4c23391d9 100644 --- a/src/cpu/simple/timing.hh +++ b/src/cpu/simple/timing.hh @@ -153,6 +153,11 @@ class TimingSimpleCPU : public BaseSimpleCPU protected: + /** + * Snooping a coherence request, do nothing. + */ + virtual bool recvTimingSnoop(PacketPtr pkt) { return true; } + TimingSimpleCPU* cpu; struct TickEvent : public Event |