2 files changed, 15 insertions, 0 deletions
diff --git a/src/cpu/simple/base.cc b/src/cpu/simple/base.cc
index 3adf6d27f..f022d05e0 100644
--- a/src/cpu/simple/base.cc
+++ b/src/cpu/simple/base.cc
@@ -286,6 +286,16 @@ BaseSimpleCPU::regStats()
         .prereq(dcacheRetryCycles)
         ;
 
+    statExecutedInstType
+        .init(Enums::Num_OpClass)
+        .name(name() + ".op_class")
+        .desc("Class of executed instruction")
+        .flags(total | pdf | dist)
+        ;
+    for (unsigned i = 0; i < Num_OpClasses; ++i) {
+        statExecutedInstType.subname(i, Enums::OpClassStrings[i]);
+    }
+
     idleFraction = constant(1.0) - notIdleFraction;
     numIdleCycles = idleFraction * numCycles;
     numBusyCycles = (notIdleFraction)*numCycles;
@@ -532,6 +542,8 @@ BaseSimpleCPU::postExecute()
     }
     /* End power model statistics */
 
+    statExecutedInstType[curStaticInst->opClass()]++;
+
     if (FullSystem)
         traceFunctions(instAddr);
 
diff --git a/src/cpu/simple/base.hh b/src/cpu/simple/base.hh
index ad672da6c..47034c300 100644
--- a/src/cpu/simple/base.hh
+++ b/src/cpu/simple/base.hh
@@ -283,6 +283,9 @@ class BaseSimpleCPU : public BaseCPU
     Stats::Scalar numBranchMispred;
     /// @}
 
+    // instruction mix histogram by OpClass
+    Stats::Vector statExecutedInstType;
+
     void serializeThread(std::ostream &os, ThreadID tid);
     void unserializeThread(Checkpoint *cp, const std::string &section,
                            ThreadID tid);