5 files changed, 23 insertions, 21 deletions
diff --git a/src/cpu/simple/atomic.cc b/src/cpu/simple/atomic.cc
index 4b243e862..cc2c3576f 100644
--- a/src/cpu/simple/atomic.cc
+++ b/src/cpu/simple/atomic.cc
@@ -68,16 +68,12 @@ AtomicSimpleCPU::TickEvent::description() const
 Port *
 AtomicSimpleCPU::getPort(const string &if_name, int idx)
 {
-    if (if_name == "dcache_port")
-        return &dcachePort;
-    else if (if_name == "icache_port")
-        return &icachePort;
-    else if (if_name == "physmem_port") {
+    if (if_name == "physmem_port") {
         hasPhysMemPort = true;
         return &physmemPort;
+    } else {
+        return BaseCPU::getPort(if_name, idx);
     }
-    else
-        panic("No Such Port\n");
 }
 
 void
diff --git a/src/cpu/simple/atomic.hh b/src/cpu/simple/atomic.hh
index f677ed49b..8a1c9000f 100644
--- a/src/cpu/simple/atomic.hh
+++ b/src/cpu/simple/atomic.hh
@@ -101,8 +101,20 @@ class AtomicSimpleCPU : public BaseSimpleCPU
 
     Range<Addr> physMemAddr;
 
+  protected:
+
+    /** Return a reference to the data port. */
+    virtual CpuPort &getDataPort() { return dcachePort; }
+
+    /** Return a reference to the instruction port. */
+    virtual CpuPort &getInstPort() { return icachePort; }
+
   public:
 
+    /**
+     * Override the getPort of the BaseCPU so that we can provide a pointer
+     * to the physmemPort, unique to the Atomic CPU.
+     */
     virtual Port *getPort(const std::string &if_name, int idx = -1);
 
     virtual void serialize(std::ostream &os);
diff --git a/src/cpu/simple/base.hh b/src/cpu/simple/base.hh
index 4c02e2eb0..4b73a4519 100644
--- a/src/cpu/simple/base.hh
+++ b/src/cpu/simple/base.hh
@@ -67,7 +67,6 @@
 
 // forward declarations
 class Checkpoint;
-class MemObject;
 class Process;
 class Processor;
 class ThreadContext;
diff --git a/src/cpu/simple/timing.cc b/src/cpu/simple/timing.cc
index d71a96580..3d1fe081d 100644
--- a/src/cpu/simple/timing.cc
+++ b/src/cpu/simple/timing.cc
@@ -60,17 +60,6 @@
 using namespace std;
 using namespace TheISA;
 
-Port *
-TimingSimpleCPU::getPort(const std::string &if_name, int idx)
-{
-    if (if_name == "dcache_port")
-        return &dcachePort;
-    else if (if_name == "icache_port")
-        return &icachePort;
-    else
-        panic("No Such Port\n");
-}
-
 void
 TimingSimpleCPU::init()
 {
diff --git a/src/cpu/simple/timing.hh b/src/cpu/simple/timing.hh
index ed91524cf..e0c5c89f7 100644
--- a/src/cpu/simple/timing.hh
+++ b/src/cpu/simple/timing.hh
@@ -231,9 +231,15 @@ class TimingSimpleCPU : public BaseSimpleCPU
 
     Tick previousTick;
 
-  public:
+  protected:
+
+     /** Return a reference to the data port. */
+    virtual CpuPort &getDataPort() { return dcachePort; }
 
-    virtual Port *getPort(const std::string &if_name, int idx = -1);
+    /** Return a reference to the instruction port. */
+    virtual CpuPort &getInstPort() { return icachePort; }
+
+  public:
 
     virtual void serialize(std::ostream &os);
     virtual void unserialize(Checkpoint *cp, const std::string &section);