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-rw-r--r--src/cpu/simple/atomic.cc5
-rw-r--r--src/cpu/simple/timing.cc15
2 files changed, 3 insertions, 17 deletions
diff --git a/src/cpu/simple/atomic.cc b/src/cpu/simple/atomic.cc
index f62f891f7..219e94043 100644
--- a/src/cpu/simple/atomic.cc
+++ b/src/cpu/simple/atomic.cc
@@ -340,9 +340,8 @@ AtomicSimpleCPU::readMem(Addr addr, uint8_t * data,
// Now do the access.
if (fault == NoFault && !req->getFlags().isSet(Request::NO_ACCESS)) {
- Packet pkt = Packet(req,
- req->isLLSC() ? MemCmd::LoadLockedReq :
- MemCmd::ReadReq);
+ Packet pkt(req, MemCmd::ReadReq);
+ pkt.refineCommand();
pkt.dataStatic(data);
if (req->isMmappedIpr())
diff --git a/src/cpu/simple/timing.cc b/src/cpu/simple/timing.cc
index 3b4f0e7d8..f572fc268 100644
--- a/src/cpu/simple/timing.cc
+++ b/src/cpu/simple/timing.cc
@@ -349,20 +349,7 @@ TimingSimpleCPU::translationFault(Fault fault)
void
TimingSimpleCPU::buildPacket(PacketPtr &pkt, RequestPtr req, bool read)
{
- MemCmd cmd;
- if (read) {
- cmd = MemCmd::ReadReq;
- if (req->isLLSC())
- cmd = MemCmd::LoadLockedReq;
- } else {
- cmd = MemCmd::WriteReq;
- if (req->isLLSC()) {
- cmd = MemCmd::StoreCondReq;
- } else if (req->isSwap()) {
- cmd = MemCmd::SwapReq;
- }
- }
- pkt = new Packet(req, cmd);
+ pkt = read ? Packet::createRead(req) : Packet::createWrite(req);
}
void