diff options
Diffstat (limited to 'src/cpu/simple')
| -rw-r--r-- | src/cpu/simple/AtomicSimpleCPU.py | 4 | ||||
| -rw-r--r-- | src/cpu/simple/TimingSimpleCPU.py | 2 |
2 files changed, 3 insertions, 3 deletions
diff --git a/src/cpu/simple/AtomicSimpleCPU.py b/src/cpu/simple/AtomicSimpleCPU.py index 3d72f4098..a4d807f86 100644 --- a/src/cpu/simple/AtomicSimpleCPU.py +++ b/src/cpu/simple/AtomicSimpleCPU.py @@ -37,5 +37,5 @@ class AtomicSimpleCPU(BaseSimpleCPU): icache_port = Port("Instruction Port") dcache_port = Port("Data Port") physmem_port = Port("Physical Memory Port") - _mem_ports = BaseSimpleCPU._mem_ports + \ - ['icache_port', 'dcache_port', 'physmem_port'] + _cached_ports = BaseSimpleCPU._cached_ports + \ + ['icache_port', 'dcache_port'] diff --git a/src/cpu/simple/TimingSimpleCPU.py b/src/cpu/simple/TimingSimpleCPU.py index 6b83c41aa..8d6888f72 100644 --- a/src/cpu/simple/TimingSimpleCPU.py +++ b/src/cpu/simple/TimingSimpleCPU.py @@ -33,4 +33,4 @@ class TimingSimpleCPU(BaseSimpleCPU): type = 'TimingSimpleCPU' icache_port = Port("Instruction Port") dcache_port = Port("Data Port") - _mem_ports = BaseSimpleCPU._mem_ports + ['icache_port', 'dcache_port'] + _cached_ports = BaseSimpleCPU._cached_ports + ['icache_port', 'dcache_port'] |