diff options
Diffstat (limited to 'src/cpu/simple')
| -rw-r--r-- | src/cpu/simple/atomic.hh | 25 | ||||
| -rw-r--r-- | src/cpu/simple/timing.hh | 10 |
2 files changed, 24 insertions, 11 deletions
diff --git a/src/cpu/simple/atomic.hh b/src/cpu/simple/atomic.hh index e3eafe8e0..9bb653bcc 100644 --- a/src/cpu/simple/atomic.hh +++ b/src/cpu/simple/atomic.hh @@ -1,5 +1,5 @@ /* - * Copyright (c) 2012 ARM Limited + * Copyright (c) 2012-2013 ARM Limited * All rights reserved. * * The license below extends only to copyright in the software and shall @@ -116,15 +116,17 @@ class AtomicSimpleCPU : public BaseSimpleCPU /** * An AtomicCPUPort overrides the default behaviour of the - * recvAtomic and ignores the packet instead of panicking. + * recvAtomicSnoop and ignores the packet instead of panicking. It + * also provides an implementation for the purely virtual timing + * functions and panics on either of these. */ - class AtomicCPUPort : public CpuPort + class AtomicCPUPort : public MasterPort { public: AtomicCPUPort(const std::string &_name, BaseCPU* _cpu) - : CpuPort(_name, _cpu) + : MasterPort(_name, _cpu) { } protected: @@ -135,6 +137,17 @@ class AtomicSimpleCPU : public BaseSimpleCPU return 0; } + bool recvTimingResp(PacketPtr pkt) + { + panic("Atomic CPU doesn't expect recvTimingResp!\n"); + return true; + } + + void recvRetry() + { + panic("Atomic CPU doesn't expect recvRetry!\n"); + } + }; AtomicCPUPort icachePort; @@ -151,10 +164,10 @@ class AtomicSimpleCPU : public BaseSimpleCPU protected: /** Return a reference to the data port. */ - virtual CpuPort &getDataPort() { return dcachePort; } + virtual MasterPort &getDataPort() { return dcachePort; } /** Return a reference to the instruction port. */ - virtual CpuPort &getInstPort() { return icachePort; } + virtual MasterPort &getInstPort() { return icachePort; } public: diff --git a/src/cpu/simple/timing.hh b/src/cpu/simple/timing.hh index 348129150..cab2057ea 100644 --- a/src/cpu/simple/timing.hh +++ b/src/cpu/simple/timing.hh @@ -1,5 +1,5 @@ /* - * Copyright (c) 2012 ARM Limited + * Copyright (c) 2012-2013 ARM Limited * All rights reserved * * The license below extends only to copyright in the software and shall @@ -152,12 +152,12 @@ class TimingSimpleCPU : public BaseSimpleCPU * scheduling of handling of incoming packets in the following * cycle. */ - class TimingCPUPort : public CpuPort + class TimingCPUPort : public MasterPort { public: TimingCPUPort(const std::string& _name, TimingSimpleCPU* _cpu) - : CpuPort(_name, _cpu), cpu(_cpu), retryEvent(this) + : MasterPort(_name, _cpu), cpu(_cpu), retryEvent(this) { } protected: @@ -248,10 +248,10 @@ class TimingSimpleCPU : public BaseSimpleCPU protected: /** Return a reference to the data port. */ - virtual CpuPort &getDataPort() { return dcachePort; } + virtual MasterPort &getDataPort() { return dcachePort; } /** Return a reference to the instruction port. */ - virtual CpuPort &getInstPort() { return icachePort; } + virtual MasterPort &getInstPort() { return icachePort; } public: |