summaryrefslogtreecommitdiff
path: root/src/cpu/simple
diff options
context:
space:
mode:
Diffstat (limited to 'src/cpu/simple')
-rw-r--r--src/cpu/simple/atomic.cc21
-rw-r--r--src/cpu/simple/base.cc41
-rw-r--r--src/cpu/simple/base.hh32
-rw-r--r--src/cpu/simple/timing.cc18
4 files changed, 41 insertions, 71 deletions
diff --git a/src/cpu/simple/atomic.cc b/src/cpu/simple/atomic.cc
index 5fcfeb7de..24e2f1eb8 100644
--- a/src/cpu/simple/atomic.cc
+++ b/src/cpu/simple/atomic.cc
@@ -42,6 +42,7 @@
#include "params/AtomicSimpleCPU.hh"
#include "sim/faults.hh"
#include "sim/system.hh"
+#include "sim/full_system.hh"
using namespace std;
using namespace TheISA;
@@ -83,18 +84,18 @@ void
AtomicSimpleCPU::init()
{
BaseCPU::init();
-#if FULL_SYSTEM
- ThreadID size = threadContexts.size();
- for (ThreadID i = 0; i < size; ++i) {
- ThreadContext *tc = threadContexts[i];
-
- // initialize CPU, including PC
- TheISA::initCPU(tc, tc->contextId());
+ if (FullSystem) {
+ ThreadID size = threadContexts.size();
+ for (ThreadID i = 0; i < size; ++i) {
+ ThreadContext *tc = threadContexts[i];
+ // initialize CPU, including PC
+ TheISA::initCPU(tc, tc->contextId());
+ }
}
// Initialise the ThreadContext's memory proxies
tcBase()->initMemProxies(tcBase());
-#endif
+
if (hasPhysMemPort) {
AddrRangeList pmAddrList = physmemPort.getPeer()->getAddrRanges();
physMemAddr = *pmAddrList.begin();
@@ -560,9 +561,7 @@ AtomicSimpleCPU *
AtomicSimpleCPUParams::create()
{
numThreads = 1;
-#if !FULL_SYSTEM
- if (workload.size() != 1)
+ if (!FullSystem && workload.size() != 1)
panic("only one workload allowed");
-#endif
return new AtomicSimpleCPU(this);
}
diff --git a/src/cpu/simple/base.cc b/src/cpu/simple/base.cc
index e56dc0fbb..97ce3264a 100644
--- a/src/cpu/simple/base.cc
+++ b/src/cpu/simple/base.cc
@@ -41,7 +41,11 @@
*/
#include "arch/faults.hh"
+#include "arch/kernel_stats.hh"
+#include "arch/stacktrace.hh"
+#include "arch/tlb.hh"
#include "arch/utility.hh"
+#include "arch/vtophys.hh"
#include "base/loader/symtab.hh"
#include "base/cp_annotate.hh"
#include "base/cprintf.hh"
@@ -64,25 +68,18 @@
#include "debug/Decode.hh"
#include "debug/Fetch.hh"
#include "debug/Quiesce.hh"
+#include "mem/mem_object.hh"
#include "mem/packet.hh"
#include "mem/request.hh"
#include "params/BaseSimpleCPU.hh"
#include "sim/byteswap.hh"
#include "sim/debug.hh"
+#include "sim/full_system.hh"
#include "sim/sim_events.hh"
#include "sim/sim_object.hh"
#include "sim/stats.hh"
#include "sim/system.hh"
-#if FULL_SYSTEM
-#include "arch/kernel_stats.hh"
-#include "arch/stacktrace.hh"
-#include "arch/tlb.hh"
-#include "arch/vtophys.hh"
-#else // !FULL_SYSTEM
-#include "mem/mem_object.hh"
-#endif // FULL_SYSTEM
-
#if USE_CHECKER
#include "cpu/checker/cpu.hh"
#include "cpu/checker/thread_context.hh"
@@ -94,12 +91,11 @@ using namespace TheISA;
BaseSimpleCPU::BaseSimpleCPU(BaseSimpleCPUParams *p)
: BaseCPU(p), traceData(NULL), thread(NULL), predecoder(NULL)
{
-#if FULL_SYSTEM
- thread = new SimpleThread(this, 0, p->system, p->itb, p->dtb);
-#else
- thread = new SimpleThread(this, /* thread_num */ 0, p->workload[0],
- p->itb, p->dtb);
-#endif // !FULL_SYSTEM
+ if (FullSystem)
+ thread = new SimpleThread(this, 0, p->system, p->itb, p->dtb);
+ else
+ thread = new SimpleThread(this, /* thread_num */ 0, p->workload[0],
+ p->itb, p->dtb);
thread->setStatus(ThreadContext::Halted);
@@ -109,9 +105,7 @@ BaseSimpleCPU::BaseSimpleCPU(BaseSimpleCPUParams *p)
if (p->checker) {
BaseCPU *temp_checker = p->checker;
checker = dynamic_cast<CheckerCPU *>(temp_checker);
-#if FULL_SYSTEM
checker->setSystem(p->system);
-#endif
// Manipulate thread context
ThreadContext *cpu_tc = tc;
tc = new CheckerThreadContext<ThreadContext>(cpu_tc, this->checker);
@@ -311,15 +305,12 @@ change_thread_state(ThreadID tid, int activate, int priority)
{
}
-#if FULL_SYSTEM
Addr
BaseSimpleCPU::dbg_vtophys(Addr addr)
{
return vtophys(tc, addr);
}
-#endif // FULL_SYSTEM
-#if FULL_SYSTEM
void
BaseSimpleCPU::wakeup()
{
@@ -329,12 +320,10 @@ BaseSimpleCPU::wakeup()
DPRINTF(Quiesce,"Suspended Processor awoke\n");
thread->activate();
}
-#endif // FULL_SYSTEM
void
BaseSimpleCPU::checkForInterrupts()
{
-#if FULL_SYSTEM
if (checkInterrupts(tc)) {
Fault interrupt = interrupts->getInterrupt(tc);
@@ -345,7 +334,6 @@ BaseSimpleCPU::checkForInterrupts()
predecoder.reset();
}
}
-#endif
}
@@ -443,15 +431,13 @@ BaseSimpleCPU::postExecute()
TheISA::PCState pc = tc->pcState();
Addr instAddr = pc.instAddr();
-#if FULL_SYSTEM
- if (thread->profile) {
+ if (FullSystem && thread->profile) {
bool usermode = TheISA::inUserMode(tc);
thread->profilePC = usermode ? 1 : instAddr;
ProfileNode *node = thread->profile->consume(tc, curStaticInst);
if (node)
thread->profileNode = node;
}
-#endif
if (curStaticInst->isMemRef()) {
numMemRefs++;
@@ -499,7 +485,8 @@ BaseSimpleCPU::postExecute()
}
/* End power model statistics */
- traceFunctions(instAddr);
+ if (FullSystem)
+ traceFunctions(instAddr);
if (traceData) {
traceData->dump();
diff --git a/src/cpu/simple/base.hh b/src/cpu/simple/base.hh
index 3535539d0..55dec5d53 100644
--- a/src/cpu/simple/base.hh
+++ b/src/cpu/simple/base.hh
@@ -47,7 +47,6 @@
#include "arch/predecoder.hh"
#include "base/statistics.hh"
-#include "config/full_system.hh"
#include "config/the_isa.hh"
#include "config/use_checker.hh"
#include "cpu/base.hh"
@@ -59,6 +58,7 @@
#include "mem/port.hh"
#include "mem/request.hh"
#include "sim/eventq.hh"
+#include "sim/full_system.hh"
#include "sim/system.hh"
#if USE_CHECKER
@@ -66,27 +66,18 @@
#endif
// forward declarations
-#if FULL_SYSTEM
-class Processor;
-namespace TheISA
-{
- class ITB;
- class DTB;
-}
+class Checkpoint;
class MemObject;
-
-#else
-
class Process;
-
-#endif // FULL_SYSTEM
+class Processor;
+class ThreadContext;
namespace TheISA
{
+ class DTB;
+ class ITB;
class Predecoder;
}
-class ThreadContext;
-class Checkpoint;
namespace Trace {
class InstRecord;
@@ -162,11 +153,9 @@ class BaseSimpleCPU : public BaseCPU
public:
-#if FULL_SYSTEM
Addr dbg_vtophys(Addr addr);
bool interval_stats;
-#endif
// current instruction
TheISA::MachInst inst;
@@ -420,19 +409,16 @@ class BaseSimpleCPU : public BaseCPU
//Fault CacheOp(uint8_t Op, Addr EA);
-#if FULL_SYSTEM
Fault hwrei() { return thread->hwrei(); }
bool simPalCheck(int palFunc) { return thread->simPalCheck(palFunc); }
-#endif
void
syscall(int64_t callnum)
{
-#if FULL_SYSTEM
- panic("Syscall emulation isn't available in FS mode.\n");
-#else
+ if (FullSystem)
+ panic("Syscall emulation isn't available in FS mode.\n");
+
thread->syscall(callnum);
-#endif
}
bool misspeculating() { return thread->misspeculating(); }
diff --git a/src/cpu/simple/timing.cc b/src/cpu/simple/timing.cc
index a0a773236..6cf7c582c 100644
--- a/src/cpu/simple/timing.cc
+++ b/src/cpu/simple/timing.cc
@@ -54,6 +54,7 @@
#include "mem/packet_access.hh"
#include "params/TimingSimpleCPU.hh"
#include "sim/faults.hh"
+#include "sim/full_system.hh"
#include "sim/system.hh"
using namespace std;
@@ -74,17 +75,16 @@ void
TimingSimpleCPU::init()
{
BaseCPU::init();
-#if FULL_SYSTEM
- for (int i = 0; i < threadContexts.size(); ++i) {
- ThreadContext *tc = threadContexts[i];
-
- // initialize CPU, including PC
- TheISA::initCPU(tc, _cpuId);
+ if (FullSystem) {
+ for (int i = 0; i < threadContexts.size(); ++i) {
+ ThreadContext *tc = threadContexts[i];
+ // initialize CPU, including PC
+ TheISA::initCPU(tc, _cpuId);
+ }
}
// Initialise the ThreadContext's memory proxies
tcBase()->initMemProxies(tcBase());
-#endif
}
void
@@ -966,9 +966,7 @@ TimingSimpleCPU *
TimingSimpleCPUParams::create()
{
numThreads = 1;
-#if !FULL_SYSTEM
- if (workload.size() != 1)
+ if (!FullSystem && workload.size() != 1)
panic("only one workload allowed");
-#endif
return new TimingSimpleCPU(this);
}
generated by cgit v1.2.3 (git 2.25.1) at 2025-01-07 23:45:54 +0000