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-rw-r--r--src/cpu/simple/timing.cc2
-rw-r--r--src/cpu/simple/timing.hh8
2 files changed, 5 insertions, 5 deletions
diff --git a/src/cpu/simple/timing.cc b/src/cpu/simple/timing.cc
index 1c468dc99..d2cb6ee21 100644
--- a/src/cpu/simple/timing.cc
+++ b/src/cpu/simple/timing.cc
@@ -80,7 +80,7 @@ TimingSimpleCPU::TimingCPUPort::TickEvent::schedule(PacketPtr _pkt, Tick t)
TimingSimpleCPU::TimingSimpleCPU(TimingSimpleCPUParams *p)
: BaseSimpleCPU(p), fetchTranslation(this), icachePort(this),
dcachePort(this), ifetch_pkt(NULL), dcache_pkt(NULL), previousCycle(0),
- fetchEvent(this)
+ fetchEvent([this]{ fetch(); }, name())
{
_status = Idle;
}
diff --git a/src/cpu/simple/timing.hh b/src/cpu/simple/timing.hh
index eebf884ca..8498630b4 100644
--- a/src/cpu/simple/timing.hh
+++ b/src/cpu/simple/timing.hh
@@ -159,7 +159,8 @@ class TimingSimpleCPU : public BaseSimpleCPU
public:
TimingCPUPort(const std::string& _name, TimingSimpleCPU* _cpu)
- : MasterPort(_name, _cpu), cpu(_cpu), retryRespEvent(this)
+ : MasterPort(_name, _cpu), cpu(_cpu),
+ retryRespEvent([this]{ sendRetryResp(); }, name())
{ }
protected:
@@ -176,7 +177,7 @@ class TimingSimpleCPU : public BaseSimpleCPU
void schedule(PacketPtr _pkt, Tick t);
};
- EventWrapper<MasterPort, &MasterPort::sendRetryResp> retryRespEvent;
+ EventFunctionWrapper retryRespEvent;
};
class IcachePort : public TimingCPUPort
@@ -315,8 +316,7 @@ class TimingSimpleCPU : public BaseSimpleCPU
private:
- typedef EventWrapper<TimingSimpleCPU, &TimingSimpleCPU::fetch> FetchEvent;
- FetchEvent fetchEvent;
+ EventFunctionWrapper fetchEvent;
struct IprEvent : Event {
Packet *pkt;