diff options
Diffstat (limited to 'src/cpu/simple')
| -rw-r--r-- | src/cpu/simple/atomic.hh | 2 | ||||
| -rw-r--r-- | src/cpu/simple/timing.cc | 8 | ||||
| -rw-r--r-- | src/cpu/simple/timing.hh | 8 |
3 files changed, 9 insertions, 9 deletions
diff --git a/src/cpu/simple/atomic.hh b/src/cpu/simple/atomic.hh index a2f3927b4..5ad5c4305 100644 --- a/src/cpu/simple/atomic.hh +++ b/src/cpu/simple/atomic.hh @@ -139,7 +139,7 @@ class AtomicSimpleCPU : public BaseSimpleCPU return true; } - void recvRetry() + void recvReqRetry() { panic("Atomic CPU doesn't expect recvRetry!\n"); } diff --git a/src/cpu/simple/timing.cc b/src/cpu/simple/timing.cc index 9171395b0..8b95696a3 100644 --- a/src/cpu/simple/timing.cc +++ b/src/cpu/simple/timing.cc @@ -729,7 +729,7 @@ TimingSimpleCPU::IcachePort::recvTimingResp(PacketPtr pkt) } void -TimingSimpleCPU::IcachePort::recvRetry() +TimingSimpleCPU::IcachePort::recvReqRetry() { // we shouldn't get a retry unless we have a packet that we're // waiting to transmit @@ -846,8 +846,8 @@ TimingSimpleCPU::DcachePort::recvTimingResp(PacketPtr pkt) // In the case of a split transaction and a cache that is // faster than a CPU we could get two responses in the // same tick, delay the second one - if (!retryEvent.scheduled()) - cpu->schedule(retryEvent, cpu->clockEdge(Cycles(1))); + if (!retryRespEvent.scheduled()) + cpu->schedule(retryRespEvent, cpu->clockEdge(Cycles(1))); return false; } } @@ -859,7 +859,7 @@ TimingSimpleCPU::DcachePort::DTickEvent::process() } void -TimingSimpleCPU::DcachePort::recvRetry() +TimingSimpleCPU::DcachePort::recvReqRetry() { // we shouldn't get a retry unless we have a packet that we're // waiting to transmit diff --git a/src/cpu/simple/timing.hh b/src/cpu/simple/timing.hh index d8460515b..3ce596fc7 100644 --- a/src/cpu/simple/timing.hh +++ b/src/cpu/simple/timing.hh @@ -157,7 +157,7 @@ class TimingSimpleCPU : public BaseSimpleCPU public: TimingCPUPort(const std::string& _name, TimingSimpleCPU* _cpu) - : MasterPort(_name, _cpu), cpu(_cpu), retryEvent(this) + : MasterPort(_name, _cpu), cpu(_cpu), retryRespEvent(this) { } protected: @@ -179,7 +179,7 @@ class TimingSimpleCPU : public BaseSimpleCPU void schedule(PacketPtr _pkt, Tick t); }; - EventWrapper<MasterPort, &MasterPort::sendRetry> retryEvent; + EventWrapper<MasterPort, &MasterPort::sendRetryResp> retryRespEvent; }; class IcachePort : public TimingCPUPort @@ -195,7 +195,7 @@ class TimingSimpleCPU : public BaseSimpleCPU virtual bool recvTimingResp(PacketPtr pkt); - virtual void recvRetry(); + virtual void recvReqRetry(); struct ITickEvent : public TickEvent { @@ -232,7 +232,7 @@ class TimingSimpleCPU : public BaseSimpleCPU virtual bool recvTimingResp(PacketPtr pkt); - virtual void recvRetry(); + virtual void recvReqRetry(); virtual bool isSnooping() const { return true; |