diff options
Diffstat (limited to 'src/cpu/simple')
-rw-r--r-- | src/cpu/simple/AtomicSimpleCPU.py | 13 | ||||
-rw-r--r-- | src/cpu/simple/TimingSimpleCPU.py | 8 |
2 files changed, 21 insertions, 0 deletions
diff --git a/src/cpu/simple/AtomicSimpleCPU.py b/src/cpu/simple/AtomicSimpleCPU.py index 1927a5862..c747582f6 100644 --- a/src/cpu/simple/AtomicSimpleCPU.py +++ b/src/cpu/simple/AtomicSimpleCPU.py @@ -42,8 +42,21 @@ from m5.params import * from BaseSimpleCPU import BaseSimpleCPU class AtomicSimpleCPU(BaseSimpleCPU): + """Simple CPU model executing a configurable number of + instructions per cycle. This model uses the simplified 'atomic' + memory mode.""" + type = 'AtomicSimpleCPU' cxx_header = "cpu/simple/atomic.hh" + + @classmethod + def memory_mode(cls): + return 'atomic' + + @classmethod + def support_take_over(cls): + return True + width = Param.Int(1, "CPU width") simulate_data_stalls = Param.Bool(False, "Simulate dcache stall cycles") simulate_inst_stalls = Param.Bool(False, "Simulate icache stall cycles") diff --git a/src/cpu/simple/TimingSimpleCPU.py b/src/cpu/simple/TimingSimpleCPU.py index 72560366e..25149eaa8 100644 --- a/src/cpu/simple/TimingSimpleCPU.py +++ b/src/cpu/simple/TimingSimpleCPU.py @@ -32,3 +32,11 @@ from BaseSimpleCPU import BaseSimpleCPU class TimingSimpleCPU(BaseSimpleCPU): type = 'TimingSimpleCPU' cxx_header = "cpu/simple/timing.hh" + + @classmethod + def memory_mode(cls): + return 'timing' + + @classmethod + def support_take_over(cls): + return True |