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-rw-r--r--src/cpu/simple/atomic.cc3
-rw-r--r--src/cpu/simple/timing.hh5
2 files changed, 5 insertions, 3 deletions
diff --git a/src/cpu/simple/atomic.cc b/src/cpu/simple/atomic.cc
index 0886b276f..fc6724939 100644
--- a/src/cpu/simple/atomic.cc
+++ b/src/cpu/simple/atomic.cc
@@ -105,7 +105,8 @@ AtomicSimpleCPU::AtomicSimpleCPU(AtomicSimpleCPUParams *p)
: BaseSimpleCPU(p), tickEvent(this), width(p->width), locked(false),
simulate_data_stalls(p->simulate_data_stalls),
simulate_inst_stalls(p->simulate_inst_stalls),
- icachePort(name() + "-iport", this), dcachePort(name() + "-iport", this),
+ icachePort(name() + ".icache_port", this),
+ dcachePort(name() + ".dcache_port", this),
fastmem(p->fastmem)
{
_status = Idle;
diff --git a/src/cpu/simple/timing.hh b/src/cpu/simple/timing.hh
index 95edea0b6..b6b78c5db 100644
--- a/src/cpu/simple/timing.hh
+++ b/src/cpu/simple/timing.hh
@@ -178,7 +178,7 @@ class TimingSimpleCPU : public BaseSimpleCPU
public:
IcachePort(TimingSimpleCPU *_cpu)
- : TimingCPUPort(_cpu->name() + "-iport", _cpu),
+ : TimingCPUPort(_cpu->name() + ".icache_port", _cpu),
tickEvent(_cpu)
{ }
@@ -206,7 +206,8 @@ class TimingSimpleCPU : public BaseSimpleCPU
public:
DcachePort(TimingSimpleCPU *_cpu)
- : TimingCPUPort(_cpu->name() + "-dport", _cpu), tickEvent(_cpu)
+ : TimingCPUPort(_cpu->name() + ".dcache_port", _cpu),
+ tickEvent(_cpu)
{ }
protected: