1 files changed, 30 insertions, 4 deletions

diff --git a/src/cpu/simple/base.hh b/src/cpu/simple/base.hh
index c39bfa9cd..c4853b916 100644
--- a/src/cpu/simple/base.hh
+++ b/src/cpu/simple/base.hh
@@ -54,15 +54,15 @@ namespace TheISA
 }
 class MemObject;
 
-class RemoteGDB;
-class GDBListener;
-
 #else
 
 class Process;
 
 #endif // FULL_SYSTEM
 
+class RemoteGDB;
+class GDBListener;
+
 class ThreadContext;
 class Checkpoint;
 
@@ -186,7 +186,8 @@ class BaseSimpleCPU : public BaseCPU
     // These functions are only used in CPU models that split
     // effective address computation from the actual memory access.
     void setEA(Addr EA) { panic("BaseSimpleCPU::setEA() not implemented\n"); }
-    Addr getEA() 	{ panic("BaseSimpleCPU::getEA() not implemented\n"); }
+    Addr getEA() 	{ panic("BaseSimpleCPU::getEA() not implemented\n");
+        M5_DUMMY_RETURN}
 
     void prefetch(Addr addr, unsigned flags)
     {
@@ -303,6 +304,31 @@ class BaseSimpleCPU : public BaseCPU
         return thread->setMiscRegWithEffect(misc_reg, val);
     }
 
+    MiscReg readMiscRegOperand(const StaticInst *si, int idx)
+    {
+        int reg_idx = si->srcRegIdx(idx) - TheISA::Ctrl_Base_DepTag;
+        return thread->readMiscReg(reg_idx);
+    }
+
+    MiscReg readMiscRegOperandWithEffect(const StaticInst *si, int idx)
+    {
+        int reg_idx = si->srcRegIdx(idx) - TheISA::Ctrl_Base_DepTag;
+        return thread->readMiscRegWithEffect(reg_idx);
+    }
+
+    void setMiscRegOperand(const StaticInst *si, int idx, const MiscReg &val)
+    {
+        int reg_idx = si->destRegIdx(idx) - TheISA::Ctrl_Base_DepTag;
+        return thread->setMiscReg(reg_idx, val);
+    }
+
+    void setMiscRegOperandWithEffect(
+            const StaticInst *si, int idx, const MiscReg &val)
+    {
+        int reg_idx = si->destRegIdx(idx) - TheISA::Ctrl_Base_DepTag;
+        return thread->setMiscRegWithEffect(reg_idx, val);
+    }
+
 #if FULL_SYSTEM
     Fault hwrei() { return thread->hwrei(); }
     void ev5_trap(Fault fault) { fault->invoke(tc); }