diff options
Diffstat (limited to 'src/cpu/simple')
| -rw-r--r-- | src/cpu/simple/base.cc | 34 | ||||
| -rw-r--r-- | src/cpu/simple/base.hh | 6 |
2 files changed, 40 insertions, 0 deletions
diff --git a/src/cpu/simple/base.cc b/src/cpu/simple/base.cc index 1611a7275..e521837df 100644 --- a/src/cpu/simple/base.cc +++ b/src/cpu/simple/base.cc @@ -503,3 +503,37 @@ BaseSimpleCPU::advancePC(Fault fault) } while (oldpc != thread->readPC()); } +Fault +BaseSimpleCPU::CacheOp(uint8_t Op, Addr EffAddr) +{ + // translate to physical address + Fault fault = NoFault; + int CacheID = Op & 0x3; // Lower 3 bits identify Cache + int CacheOP = Op >> 2; // Upper 3 bits identify Cache Operation + if(CacheID > 1) + { + warn("CacheOps not implemented for secondary/tertiary caches\n"); + } + else + { + switch(CacheOP) + { // Fill Packet Type + case 0: warn("Invalidate Cache Op\n"); + break; + case 1: warn("Index Load Tag Cache Op\n"); + break; + case 2: warn("Index Store Tag Cache Op\n"); + break; + case 4: warn("Hit Invalidate Cache Op\n"); + break; + case 5: warn("Fill/Hit Writeback Invalidate Cache Op\n"); + break; + case 6: warn("Hit Writeback\n"); + break; + case 7: warn("Fetch & Lock Cache Op\n"); + break; + default: warn("Unimplemented Cache Op\n"); + } + } + return fault; +} diff --git a/src/cpu/simple/base.hh b/src/cpu/simple/base.hh index 337ef5285..5990e46b0 100644 --- a/src/cpu/simple/base.hh +++ b/src/cpu/simple/base.hh @@ -378,6 +378,12 @@ class BaseSimpleCPU : public BaseCPU "register access.\n"); } + void setShadowSet(int css) { + panic("Simple CPU models do not support Shadow Sets"); + //tc->setShadowSet(css); + } + + Fault CacheOp(uint8_t Op, Addr EA); #if FULL_SYSTEM Fault hwrei() { return thread->hwrei(); } void ev5_trap(Fault fault) { fault->invoke(tc); } |