diff options
Diffstat (limited to 'src/cpu/simple')
| -rw-r--r-- | src/cpu/simple/AtomicSimpleCPU.py | 1 | ||||
| -rw-r--r-- | src/cpu/simple/BaseSimpleCPU.py | 1 | ||||
| -rw-r--r-- | src/cpu/simple/TimingSimpleCPU.py | 1 |
3 files changed, 3 insertions, 0 deletions
diff --git a/src/cpu/simple/AtomicSimpleCPU.py b/src/cpu/simple/AtomicSimpleCPU.py index 54daaec63..1927a5862 100644 --- a/src/cpu/simple/AtomicSimpleCPU.py +++ b/src/cpu/simple/AtomicSimpleCPU.py @@ -43,6 +43,7 @@ from BaseSimpleCPU import BaseSimpleCPU class AtomicSimpleCPU(BaseSimpleCPU): type = 'AtomicSimpleCPU' + cxx_header = "cpu/simple/atomic.hh" width = Param.Int(1, "CPU width") simulate_data_stalls = Param.Bool(False, "Simulate dcache stall cycles") simulate_inst_stalls = Param.Bool(False, "Simulate icache stall cycles") diff --git a/src/cpu/simple/BaseSimpleCPU.py b/src/cpu/simple/BaseSimpleCPU.py index d9b963890..a4ae7e34b 100644 --- a/src/cpu/simple/BaseSimpleCPU.py +++ b/src/cpu/simple/BaseSimpleCPU.py @@ -34,6 +34,7 @@ from DummyChecker import DummyChecker class BaseSimpleCPU(BaseCPU): type = 'BaseSimpleCPU' abstract = True + cxx_header = "cpu/simple/base.hh" def addCheckerCpu(self): if buildEnv['TARGET_ISA'] in ['arm']: diff --git a/src/cpu/simple/TimingSimpleCPU.py b/src/cpu/simple/TimingSimpleCPU.py index 61491b087..72560366e 100644 --- a/src/cpu/simple/TimingSimpleCPU.py +++ b/src/cpu/simple/TimingSimpleCPU.py @@ -31,3 +31,4 @@ from BaseSimpleCPU import BaseSimpleCPU class TimingSimpleCPU(BaseSimpleCPU): type = 'TimingSimpleCPU' + cxx_header = "cpu/simple/timing.hh" |