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-rw-r--r--src/cpu/simple/AtomicSimpleCPU.py4
-rw-r--r--src/cpu/simple/TimingSimpleCPU.py3
-rw-r--r--src/cpu/simple/atomic.cc65
-rw-r--r--src/cpu/simple/atomic.hh46
-rw-r--r--src/cpu/simple/timing.cc53
-rw-r--r--src/cpu/simple/timing.hh45
6 files changed, 44 insertions, 172 deletions
diff --git a/src/cpu/simple/AtomicSimpleCPU.py b/src/cpu/simple/AtomicSimpleCPU.py
index a4d807f86..93cd02ba7 100644
--- a/src/cpu/simple/AtomicSimpleCPU.py
+++ b/src/cpu/simple/AtomicSimpleCPU.py
@@ -34,8 +34,4 @@ class AtomicSimpleCPU(BaseSimpleCPU):
width = Param.Int(1, "CPU width")
simulate_data_stalls = Param.Bool(False, "Simulate dcache stall cycles")
simulate_inst_stalls = Param.Bool(False, "Simulate icache stall cycles")
- icache_port = Port("Instruction Port")
- dcache_port = Port("Data Port")
physmem_port = Port("Physical Memory Port")
- _cached_ports = BaseSimpleCPU._cached_ports + \
- ['icache_port', 'dcache_port']
diff --git a/src/cpu/simple/TimingSimpleCPU.py b/src/cpu/simple/TimingSimpleCPU.py
index 8d6888f72..61491b087 100644
--- a/src/cpu/simple/TimingSimpleCPU.py
+++ b/src/cpu/simple/TimingSimpleCPU.py
@@ -31,6 +31,3 @@ from BaseSimpleCPU import BaseSimpleCPU
class TimingSimpleCPU(BaseSimpleCPU):
type = 'TimingSimpleCPU'
- icache_port = Port("Instruction Port")
- dcache_port = Port("Data Port")
- _cached_ports = BaseSimpleCPU._cached_ports + ['icache_port', 'dcache_port']
diff --git a/src/cpu/simple/atomic.cc b/src/cpu/simple/atomic.cc
index fed94ffd8..2c12b244b 100644
--- a/src/cpu/simple/atomic.cc
+++ b/src/cpu/simple/atomic.cc
@@ -92,10 +92,12 @@ AtomicSimpleCPU::init()
TheISA::initCPU(tc, tc->contextId());
}
}
+
+ // Initialise the ThreadContext's memory proxies
+ tcBase()->initMemProxies(tcBase());
+
if (hasPhysMemPort) {
- bool snoop = false;
- AddrRangeList pmAddrList;
- physmemPort.getPeerAddressRanges(pmAddrList, snoop);
+ AddrRangeList pmAddrList = physmemPort.getPeer()->getAddrRanges();
physMemAddr = *pmAddrList.begin();
}
// Atomic doesn't do MT right now, so contextId == threadId
@@ -104,59 +106,6 @@ AtomicSimpleCPU::init()
data_write_req.setThreadContext(_cpuId, 0); // Add thread ID here too
}
-bool
-AtomicSimpleCPU::CpuPort::recvTiming(PacketPtr pkt)
-{
- panic("AtomicSimpleCPU doesn't expect recvTiming callback!");
- return true;
-}
-
-Tick
-AtomicSimpleCPU::CpuPort::recvAtomic(PacketPtr pkt)
-{
- //Snooping a coherence request, just return
- return 0;
-}
-
-void
-AtomicSimpleCPU::CpuPort::recvFunctional(PacketPtr pkt)
-{
- //No internal storage to update, just return
- return;
-}
-
-void
-AtomicSimpleCPU::CpuPort::recvStatusChange(Status status)
-{
- if (status == RangeChange) {
- if (!snoopRangeSent) {
- snoopRangeSent = true;
- sendStatusChange(Port::RangeChange);
- }
- return;
- }
-
- panic("AtomicSimpleCPU doesn't expect recvStatusChange callback!");
-}
-
-void
-AtomicSimpleCPU::CpuPort::recvRetry()
-{
- panic("AtomicSimpleCPU doesn't expect recvRetry callback!");
-}
-
-void
-AtomicSimpleCPU::DcachePort::setPeer(Port *port)
-{
- Port::setPeer(port);
-
- if (FullSystem) {
- // Update the ThreadContext's memory ports (Functional/Virtual
- // Ports)
- cpu->tcBase()->connectMemPorts(cpu->tcBase());
- }
-}
-
AtomicSimpleCPU::AtomicSimpleCPU(AtomicSimpleCPUParams *p)
: BaseSimpleCPU(p), tickEvent(this), width(p->width), locked(false),
simulate_data_stalls(p->simulate_data_stalls),
@@ -165,10 +114,6 @@ AtomicSimpleCPU::AtomicSimpleCPU(AtomicSimpleCPUParams *p)
physmemPort(name() + "-iport", this), hasPhysMemPort(false)
{
_status = Idle;
-
- icachePort.snoopRangeSent = false;
- dcachePort.snoopRangeSent = false;
-
}
diff --git a/src/cpu/simple/atomic.hh b/src/cpu/simple/atomic.hh
index 246afa0b2..77a9d6b0d 100644
--- a/src/cpu/simple/atomic.hh
+++ b/src/cpu/simple/atomic.hh
@@ -64,47 +64,31 @@ class AtomicSimpleCPU : public BaseSimpleCPU
// main simulation loop (one cycle)
void tick();
- class CpuPort : public Port
+ /**
+ * An AtomicCPUPort overrides the default behaviour of the
+ * recvAtomic and ignores the packet instead of panicking.
+ */
+ class AtomicCPUPort : public CpuPort
{
+
public:
- CpuPort(const std::string &_name, AtomicSimpleCPU *_cpu)
- : Port(_name, _cpu), cpu(_cpu)
+ AtomicCPUPort(const std::string &_name, BaseCPU* _cpu)
+ : CpuPort(_name, _cpu)
{ }
- bool snoopRangeSent;
-
protected:
- AtomicSimpleCPU *cpu;
-
- virtual bool recvTiming(PacketPtr pkt);
-
- virtual Tick recvAtomic(PacketPtr pkt);
-
- virtual void recvFunctional(PacketPtr pkt);
-
- virtual void recvStatusChange(Status status);
-
- virtual void recvRetry();
-
- virtual void getDeviceAddressRanges(AddrRangeList &resp,
- bool &snoop)
- { resp.clear(); snoop = true; }
+ virtual Tick recvAtomic(PacketPtr pkt)
+ {
+ // Snooping a coherence request, just return
+ return 0;
+ }
};
- CpuPort icachePort;
- class DcachePort : public CpuPort
- {
- public:
- DcachePort(const std::string &_name, AtomicSimpleCPU *_cpu)
- : CpuPort(_name, _cpu)
- { }
-
- virtual void setPeer(Port *port);
- };
- DcachePort dcachePort;
+ AtomicCPUPort icachePort;
+ AtomicCPUPort dcachePort;
CpuPort physmemPort;
bool hasPhysMemPort;
diff --git a/src/cpu/simple/timing.cc b/src/cpu/simple/timing.cc
index 983672c27..fd02e8300 100644
--- a/src/cpu/simple/timing.cc
+++ b/src/cpu/simple/timing.cc
@@ -82,53 +82,24 @@ TimingSimpleCPU::init()
TheISA::initCPU(tc, _cpuId);
}
}
-}
-
-Tick
-TimingSimpleCPU::CpuPort::recvAtomic(PacketPtr pkt)
-{
- panic("TimingSimpleCPU doesn't expect recvAtomic callback!");
- return curTick();
-}
-void
-TimingSimpleCPU::CpuPort::recvFunctional(PacketPtr pkt)
-{
- //No internal storage to update, jusst return
- return;
+ // Initialise the ThreadContext's memory proxies
+ tcBase()->initMemProxies(tcBase());
}
void
-TimingSimpleCPU::CpuPort::recvStatusChange(Status status)
-{
- if (status == RangeChange) {
- if (!snoopRangeSent) {
- snoopRangeSent = true;
- sendStatusChange(Port::RangeChange);
- }
- return;
- }
-
- panic("TimingSimpleCPU doesn't expect recvStatusChange callback!");
-}
-
-
-void
-TimingSimpleCPU::CpuPort::TickEvent::schedule(PacketPtr _pkt, Tick t)
+TimingSimpleCPU::TimingCPUPort::TickEvent::schedule(PacketPtr _pkt, Tick t)
{
pkt = _pkt;
cpu->schedule(this, t);
}
TimingSimpleCPU::TimingSimpleCPU(TimingSimpleCPUParams *p)
- : BaseSimpleCPU(p), fetchTranslation(this), icachePort(this, p->clock),
- dcachePort(this, p->clock), fetchEvent(this)
+ : BaseSimpleCPU(p), fetchTranslation(this), icachePort(this),
+ dcachePort(this), fetchEvent(this)
{
_status = Idle;
- icachePort.snoopRangeSent = false;
- dcachePort.snoopRangeSent = false;
-
ifetch_pkt = dcache_pkt = NULL;
drainEvent = NULL;
previousTick = 0;
@@ -874,18 +845,6 @@ TimingSimpleCPU::completeDrain()
drainEvent->process();
}
-void
-TimingSimpleCPU::DcachePort::setPeer(Port *port)
-{
- Port::setPeer(port);
-
- if (FullSystem) {
- // Update the ThreadContext's memory ports (Functional/Virtual
- // Ports)
- cpu->tcBase()->connectMemPorts(cpu->tcBase());
- }
-}
-
bool
TimingSimpleCPU::DcachePort::recvTiming(PacketPtr pkt)
{
@@ -903,7 +862,7 @@ TimingSimpleCPU::DcachePort::recvTiming(PacketPtr pkt)
// faster than a CPU we could get two responses before
// next_tick expires
if (!retryEvent.scheduled())
- schedule(retryEvent, next_tick);
+ cpu->schedule(retryEvent, next_tick);
return false;
}
}
diff --git a/src/cpu/simple/timing.hh b/src/cpu/simple/timing.hh
index 4301dfca7..dce3c58ff 100644
--- a/src/cpu/simple/timing.hh
+++ b/src/cpu/simple/timing.hh
@@ -137,31 +137,23 @@ class TimingSimpleCPU : public BaseSimpleCPU
// This function always implicitly uses dcache_pkt.
bool handleWritePacket();
- class CpuPort : public Port
+ /**
+ * A TimingCPUPort overrides the default behaviour of the
+ * recvTiming and recvRetry and implements events for the
+ * scheduling of handling of incoming packets in the following
+ * cycle.
+ */
+ class TimingCPUPort : public CpuPort
{
- protected:
- TimingSimpleCPU *cpu;
- Tick lat;
-
public:
- CpuPort(const std::string &_name, TimingSimpleCPU *_cpu, Tick _lat)
- : Port(_name, _cpu), cpu(_cpu), lat(_lat), retryEvent(this)
+ TimingCPUPort(const std::string& _name, TimingSimpleCPU* _cpu)
+ : CpuPort(_name, _cpu), cpu(_cpu), retryEvent(this)
{ }
- bool snoopRangeSent;
-
protected:
- virtual Tick recvAtomic(PacketPtr pkt);
-
- virtual void recvFunctional(PacketPtr pkt);
-
- virtual void recvStatusChange(Status status);
-
- virtual void getDeviceAddressRanges(AddrRangeList &resp,
- bool &snoop)
- { resp.clear(); snoop = false; }
+ TimingSimpleCPU* cpu;
struct TickEvent : public Event
{
@@ -169,7 +161,7 @@ class TimingSimpleCPU : public BaseSimpleCPU
TimingSimpleCPU *cpu;
CpuPort *port;
- TickEvent(TimingSimpleCPU *_cpu) : cpu(_cpu) {}
+ TickEvent(TimingSimpleCPU *_cpu) : pkt(NULL), cpu(_cpu) {}
const char *description() const { return "Timing CPU tick"; }
void schedule(PacketPtr _pkt, Tick t);
};
@@ -177,12 +169,13 @@ class TimingSimpleCPU : public BaseSimpleCPU
EventWrapper<Port, &Port::sendRetry> retryEvent;
};
- class IcachePort : public CpuPort
+ class IcachePort : public TimingCPUPort
{
public:
- IcachePort(TimingSimpleCPU *_cpu, Tick _lat)
- : CpuPort(_cpu->name() + "-iport", _cpu, _lat), tickEvent(_cpu)
+ IcachePort(TimingSimpleCPU *_cpu)
+ : TimingCPUPort(_cpu->name() + "-iport", _cpu),
+ tickEvent(_cpu)
{ }
protected:
@@ -204,16 +197,14 @@ class TimingSimpleCPU : public BaseSimpleCPU
};
- class DcachePort : public CpuPort
+ class DcachePort : public TimingCPUPort
{
public:
- DcachePort(TimingSimpleCPU *_cpu, Tick _lat)
- : CpuPort(_cpu->name() + "-dport", _cpu, _lat), tickEvent(_cpu)
+ DcachePort(TimingSimpleCPU *_cpu)
+ : TimingCPUPort(_cpu->name() + "-dport", _cpu), tickEvent(_cpu)
{ }
- virtual void setPeer(Port *port);
-
protected:
virtual bool recvTiming(PacketPtr pkt);
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-02 04:57:17 +0000