2 files changed, 9 insertions, 8 deletions
diff --git a/src/cpu/simple/atomic.cc b/src/cpu/simple/atomic.cc
index e5b3bd67d..d7ad07a5e 100644
--- a/src/cpu/simple/atomic.cc
+++ b/src/cpu/simple/atomic.cc
@@ -65,14 +65,14 @@ AtomicSimpleCPU::TickEvent::description() const
     return "AtomicSimpleCPU tick";
 }
 
-Port *
-AtomicSimpleCPU::getPort(const string &if_name, int idx)
+MasterPort &
+AtomicSimpleCPU::getMasterPort(const string &if_name, int idx)
 {
     if (if_name == "physmem_port") {
         hasPhysMemPort = true;
-        return &physmemPort;
+        return physmemPort;
     } else {
-        return BaseCPU::getPort(if_name, idx);
+        return BaseCPU::getMasterPort(if_name, idx);
     }
 }
 
@@ -94,7 +94,7 @@ AtomicSimpleCPU::init()
     }
 
     if (hasPhysMemPort) {
-        AddrRangeList pmAddrList = physmemPort.getPeer()->getAddrRanges();
+        AddrRangeList pmAddrList = physmemPort.getSlavePort().getAddrRanges();
         physMemAddr = *pmAddrList.begin();
     }
     // Atomic doesn't do MT right now, so contextId == threadId
diff --git a/src/cpu/simple/atomic.hh b/src/cpu/simple/atomic.hh
index 8a1c9000f..126cd3765 100644
--- a/src/cpu/simple/atomic.hh
+++ b/src/cpu/simple/atomic.hh
@@ -112,10 +112,11 @@ class AtomicSimpleCPU : public BaseSimpleCPU
   public:
 
     /**
-     * Override the getPort of the BaseCPU so that we can provide a pointer
-     * to the physmemPort, unique to the Atomic CPU.
+     * Override the getMasterPort of the BaseCPU so that we can
+     * provide the physmemPort, unique to the Atomic CPU.
      */
-    virtual Port *getPort(const std::string &if_name, int idx = -1);
+    virtual MasterPort &getMasterPort(const std::string &if_name,
+                                      int idx = -1);
 
     virtual void serialize(std::ostream &os);
     virtual void unserialize(Checkpoint *cp, const std::string &section);