diff options
Diffstat (limited to 'src/cpu/simple')
| -rw-r--r-- | src/cpu/simple/atomic.cc | 7 | ||||
| -rw-r--r-- | src/cpu/simple/timing.cc | 2 |
2 files changed, 3 insertions, 6 deletions
diff --git a/src/cpu/simple/atomic.cc b/src/cpu/simple/atomic.cc index eea7615c8..f3596b6a5 100644 --- a/src/cpu/simple/atomic.cc +++ b/src/cpu/simple/atomic.cc @@ -430,7 +430,7 @@ AtomicSimpleCPU::writeMem(uint8_t *data, unsigned size, Addr addr, if (data == NULL) { assert(size <= 64); - assert(flags & Request::CACHE_BLOCK_ZERO); + assert(flags & Request::STORE_NO_DATA); // This must be a cache block cleaning request data = zero_array; } @@ -462,14 +462,11 @@ AtomicSimpleCPU::writeMem(uint8_t *data, unsigned size, Addr addr, // Now do the access. if (fault == NoFault) { - MemCmd cmd = MemCmd::WriteReq; // default bool do_access = true; // flag to suppress cache access if (req->isLLSC()) { - cmd = MemCmd::StoreCondReq; do_access = TheISA::handleLockedWrite(thread, req, dcachePort.cacheBlockMask); } else if (req->isSwap()) { - cmd = MemCmd::SwapReq; if (req->isCondSwap()) { assert(res); req->setExtraData(*res); @@ -477,7 +474,7 @@ AtomicSimpleCPU::writeMem(uint8_t *data, unsigned size, Addr addr, } if (do_access && !req->getFlags().isSet(Request::NO_ACCESS)) { - Packet pkt = Packet(req, cmd); + Packet pkt(req, Packet::makeWriteCmd(req)); pkt.dataStatic(data); if (req->isMmappedIpr()) { diff --git a/src/cpu/simple/timing.cc b/src/cpu/simple/timing.cc index c38f2107f..961e31935 100644 --- a/src/cpu/simple/timing.cc +++ b/src/cpu/simple/timing.cc @@ -510,7 +510,7 @@ TimingSimpleCPU::writeMem(uint8_t *data, unsigned size, BaseTLB::Mode mode = BaseTLB::Write; if (data == NULL) { - assert(flags & Request::CACHE_BLOCK_ZERO); + assert(flags & Request::STORE_NO_DATA); // This must be a cache block cleaning request memset(newData, 0, size); } else { |