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-rw-r--r--src/cpu/simple/atomic.cc15
-rw-r--r--src/cpu/simple/timing.cc18
2 files changed, 15 insertions, 18 deletions
diff --git a/src/cpu/simple/atomic.cc b/src/cpu/simple/atomic.cc
index a8e97f14c..f3e14d401 100644
--- a/src/cpu/simple/atomic.cc
+++ b/src/cpu/simple/atomic.cc
@@ -87,9 +87,9 @@ AtomicSimpleCPU::init()
BaseSimpleCPU::init();
int cid = threadContexts[0]->contextId();
- ifetch_req.setContext(cid);
- data_read_req.setContext(cid);
- data_write_req.setContext(cid);
+ ifetch_req.setThreadContext(cid, 0);
+ data_read_req.setThreadContext(cid, 0);
+ data_write_req.setThreadContext(cid, 0);
}
AtomicSimpleCPU::AtomicSimpleCPU(AtomicSimpleCPUParams *p)
@@ -247,8 +247,6 @@ AtomicSimpleCPU::activateContext(ThreadID thread_num)
== activeThreads.end()) {
activeThreads.push_back(thread_num);
}
-
- BaseCPU::activateContext(thread_num);
}
@@ -275,7 +273,6 @@ AtomicSimpleCPU::suspendContext(ThreadID thread_num)
}
}
- BaseCPU::suspendContext(thread_num);
}
@@ -557,9 +554,9 @@ AtomicSimpleCPU::tick()
if (numThreads > 1) {
ContextID cid = threadContexts[curThread]->contextId();
- ifetch_req.setContext(cid);
- data_read_req.setContext(cid);
- data_write_req.setContext(cid);
+ ifetch_req.setThreadContext(cid, curThread);
+ data_read_req.setThreadContext(cid, curThread);
+ data_write_req.setThreadContext(cid, curThread);
}
SimpleExecContext& t_info = *threadInfo[curThread];
diff --git a/src/cpu/simple/timing.cc b/src/cpu/simple/timing.cc
index 515d6b23c..43f4eb9f4 100644
--- a/src/cpu/simple/timing.cc
+++ b/src/cpu/simple/timing.cc
@@ -218,8 +218,6 @@ TimingSimpleCPU::activateContext(ThreadID thread_num)
== activeThreads.end()) {
activeThreads.push_back(thread_num);
}
-
- BaseCPU::activateContext(thread_num);
}
@@ -245,8 +243,6 @@ TimingSimpleCPU::suspendContext(ThreadID thread_num)
deschedule(fetchEvent);
}
}
-
- BaseCPU::suspendContext(thread_num);
}
bool
@@ -423,6 +419,7 @@ TimingSimpleCPU::initiateMemRead(Addr addr, unsigned size, unsigned flags)
Fault fault;
const int asid = 0;
+ const ThreadID tid = curThread;
const Addr pc = thread->instAddr();
unsigned block_size = cacheLineSize();
BaseTLB::Mode mode = BaseTLB::Read;
@@ -430,8 +427,9 @@ TimingSimpleCPU::initiateMemRead(Addr addr, unsigned size, unsigned flags)
if (traceData)
traceData->setMem(addr, size, flags);
- RequestPtr req = new Request(asid, addr, size, flags, dataMasterId(), pc,
- thread->contextId());
+ RequestPtr req = new Request(asid, addr, size,
+ flags, dataMasterId(), pc,
+ thread->contextId(), tid);
req->taskId(taskId());
@@ -496,6 +494,7 @@ TimingSimpleCPU::writeMem(uint8_t *data, unsigned size,
uint8_t *newData = new uint8_t[size];
const int asid = 0;
+ const ThreadID tid = curThread;
const Addr pc = thread->instAddr();
unsigned block_size = cacheLineSize();
BaseTLB::Mode mode = BaseTLB::Write;
@@ -511,8 +510,9 @@ TimingSimpleCPU::writeMem(uint8_t *data, unsigned size,
if (traceData)
traceData->setMem(addr, size, flags);
- RequestPtr req = new Request(asid, addr, size, flags, dataMasterId(), pc,
- thread->contextId());
+ RequestPtr req = new Request(asid, addr, size,
+ flags, dataMasterId(), pc,
+ thread->contextId(), tid);
req->taskId(taskId());
@@ -614,7 +614,7 @@ TimingSimpleCPU::fetch()
_status = BaseSimpleCPU::Running;
Request *ifetch_req = new Request();
ifetch_req->taskId(taskId());
- ifetch_req->setContext(thread->contextId());
+ ifetch_req->setThreadContext(thread->contextId(), curThread);
setupFetchRequest(ifetch_req);
DPRINTF(SimpleCPU, "Translating address %#x\n", ifetch_req->getVaddr());
thread->itb->translateTiming(ifetch_req, thread->getTC(),