diff options
Diffstat (limited to 'src/cpu/testers/directedtest')
| -rw-r--r-- | src/cpu/testers/directedtest/DirectedGenerator.cc | 44 | ||||
| -rw-r--r-- | src/cpu/testers/directedtest/DirectedGenerator.hh | 56 | ||||
| -rw-r--r-- | src/cpu/testers/directedtest/InvalidateGenerator.cc | 142 | ||||
| -rw-r--r-- | src/cpu/testers/directedtest/InvalidateGenerator.hh | 63 | ||||
| -rw-r--r-- | src/cpu/testers/directedtest/RubyDirectedTester.cc | 136 | ||||
| -rw-r--r-- | src/cpu/testers/directedtest/RubyDirectedTester.hh | 118 | ||||
| -rw-r--r-- | src/cpu/testers/directedtest/RubyDirectedTester.py | 52 | ||||
| -rw-r--r-- | src/cpu/testers/directedtest/SConscript | 48 | ||||
| -rw-r--r-- | src/cpu/testers/directedtest/SeriesRequestGenerator.cc | 114 | ||||
| -rw-r--r-- | src/cpu/testers/directedtest/SeriesRequestGenerator.hh | 63 |
10 files changed, 836 insertions, 0 deletions
diff --git a/src/cpu/testers/directedtest/DirectedGenerator.cc b/src/cpu/testers/directedtest/DirectedGenerator.cc new file mode 100644 index 000000000..68ea55449 --- /dev/null +++ b/src/cpu/testers/directedtest/DirectedGenerator.cc @@ -0,0 +1,44 @@ +/* + * Copyright (c) 1999-2008 Mark D. Hill and David A. Wood + * Copyright (c) 2009-2010 Advanced Micro Devices, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer; + * redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution; + * neither the name of the copyright holders nor the names of its + * contributors may be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include "cpu/testers/directedtest/DirectedGenerator.hh" + +DirectedGenerator::DirectedGenerator(const Params *p) + : SimObject(p) +{ + m_num_cpus = p->num_cpus; + m_directed_tester = NULL; +} + +void +DirectedGenerator::setDirectedTester(RubyDirectedTester* directed_tester) +{ + assert(m_directed_tester == NULL); + m_directed_tester = directed_tester; +} diff --git a/src/cpu/testers/directedtest/DirectedGenerator.hh b/src/cpu/testers/directedtest/DirectedGenerator.hh new file mode 100644 index 000000000..904dcf399 --- /dev/null +++ b/src/cpu/testers/directedtest/DirectedGenerator.hh @@ -0,0 +1,56 @@ +/* + * Copyright (c) 1999-2008 Mark D. Hill and David A. Wood + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer; + * redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution; + * neither the name of the copyright holders nor the names of its + * contributors may be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef __CPU_DIRECTEDTEST_DIRECTEDGENERATOR_HH__ +#define __CPU_DIRECTEDTEST_DIRECTEDGENERATOR_HH__ + +#include "cpu/testers/directedtest/DirectedGenerator.hh" +#include "cpu/testers/directedtest/RubyDirectedTester.hh" +#include "params/DirectedGenerator.hh" +#include "sim/sim_object.hh" + +class DirectedGenerator : public SimObject +{ + public: + typedef DirectedGeneratorParams Params; + DirectedGenerator(const Params *p); + + virtual ~DirectedGenerator() {} + + virtual bool initiate() = 0; + virtual void performCallback(uint proc, Addr address) = 0; + + void setDirectedTester(RubyDirectedTester* directed_tester); + + protected: + int m_num_cpus; + RubyDirectedTester* m_directed_tester; +}; + +#endif //__CPU_DIRECTEDTEST_DIRECTEDGENERATOR_HH__ + diff --git a/src/cpu/testers/directedtest/InvalidateGenerator.cc b/src/cpu/testers/directedtest/InvalidateGenerator.cc new file mode 100644 index 000000000..724702d61 --- /dev/null +++ b/src/cpu/testers/directedtest/InvalidateGenerator.cc @@ -0,0 +1,142 @@ +/* + * Copyright (c) 1999-2008 Mark D. Hill and David A. Wood + * Copyright (c) 2009-2010 Advanced Micro Devices, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer; + * redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution; + * neither the name of the copyright holders nor the names of its + * contributors may be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include "cpu/testers/directedtest/RubyDirectedTester.hh" +#include "cpu/testers/directedtest/DirectedGenerator.hh" +#include "cpu/testers/directedtest/InvalidateGenerator.hh" + +InvalidateGenerator::InvalidateGenerator(const Params *p) + : DirectedGenerator(p) +{ + // + // First, issue loads to bring the block into S state + // + m_status = InvalidateGeneratorStatus_Load_Waiting; + m_active_read_node = 0; + m_active_inv_node = 0; + m_address = 0x0; + m_addr_increment_size = p->addr_increment_size; +} + +InvalidateGenerator::~InvalidateGenerator() +{ +} + +bool +InvalidateGenerator::initiate() +{ + RubyDirectedTester::CpuPort* port; + Request::Flags flags; + PacketPtr pkt; + Packet::Command cmd; + + // For simplicity, requests are assumed to be 1 byte-sized + Request *req = new Request(m_address, 1, flags); + + // + // Based on the current state, issue a load or a store + // + if (m_status == InvalidateGeneratorStatus_Load_Waiting) { + DPRINTF(DirectedTest, "initiating read\n"); + cmd = MemCmd::ReadReq; + port = safe_cast<RubyDirectedTester::CpuPort*>(m_directed_tester-> + getCpuPort(m_active_read_node)); + pkt = new Packet(req, cmd, m_active_read_node); + } else if (m_status == InvalidateGeneratorStatus_Inv_Waiting) { + DPRINTF(DirectedTest, "initiating invalidating write\n"); + cmd = MemCmd::WriteReq; + port = safe_cast<RubyDirectedTester::CpuPort*>(m_directed_tester-> + getCpuPort(m_active_inv_node)); + pkt = new Packet(req, cmd, m_active_inv_node); + } else { + panic("initiate was unexpectedly called\n"); + } + uint8_t* dummyData = new uint8_t; + *dummyData = 0; + pkt->dataDynamic(dummyData); + + if (port->sendTiming(pkt)) { + DPRINTF(DirectedTest, "initiating request - successful\n"); + if (m_status == InvalidateGeneratorStatus_Load_Waiting) { + m_status = InvalidateGeneratorStatus_Load_Pending; + } else { + m_status = InvalidateGeneratorStatus_Inv_Pending; + } + return true; + } else { + // If the packet did not issue, must delete + // Note: No need to delete the data, the packet destructor + // will delete it + delete pkt->req; + delete pkt; + + DPRINTF(DirectedTest, "failed to issue request - sequencer not ready\n"); + return false; + } +} + +void +InvalidateGenerator::performCallback(uint proc, Addr address) +{ + assert(m_address == address); + + if (m_status == InvalidateGeneratorStatus_Load_Pending) { + assert(m_active_read_node == proc); + m_active_read_node++; + // + // Once all cpus have the block in S state, issue the invalidate + // + if (m_active_read_node == m_num_cpus) { + m_status = InvalidateGeneratorStatus_Inv_Waiting; + m_active_read_node = 0; + } else { + m_status = InvalidateGeneratorStatus_Load_Waiting; + } + } else if (m_status == InvalidateGeneratorStatus_Inv_Pending) { + assert(m_active_inv_node == proc); + m_active_inv_node++; + if (m_active_inv_node == m_num_cpus) { + m_address += m_addr_increment_size; + m_active_inv_node = 0; + } + // + // Invalidate completed, send that info to the tester and restart + // the cycle + // + m_directed_tester->incrementCycleCompletions(); + m_status = InvalidateGeneratorStatus_Load_Waiting; + } + +} + +InvalidateGenerator * +InvalidateGeneratorParams::create() +{ + return new InvalidateGenerator(this); +} diff --git a/src/cpu/testers/directedtest/InvalidateGenerator.hh b/src/cpu/testers/directedtest/InvalidateGenerator.hh new file mode 100644 index 000000000..ab68c859f --- /dev/null +++ b/src/cpu/testers/directedtest/InvalidateGenerator.hh @@ -0,0 +1,63 @@ +/* + * Copyright (c) 1999-2008 Mark D. Hill and David A. Wood + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer; + * redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution; + * neither the name of the copyright holders nor the names of its + * contributors may be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +// +// This Directed Generator generates GETX requests for all nodes in the +// system. The GETX requests are generated one at a time in round-robin fashion +// 0...1...2...etc. +// + +#ifndef __CPU_DIRECTEDTEST_INVALIDATEGENERATOR_HH__ +#define __CPU_DIRECTEDTEST_INVALIDATEGENERATOR_HH__ + +#include "cpu/testers/directedtest/RubyDirectedTester.hh" +#include "cpu/testers/directedtest/DirectedGenerator.hh" +#include "mem/protocol/InvalidateGeneratorStatus.hh" +#include "params/InvalidateGenerator.hh" + +class InvalidateGenerator : public DirectedGenerator +{ + public: + typedef InvalidateGeneratorParams Params; + InvalidateGenerator(const Params *p); + + ~InvalidateGenerator(); + + bool initiate(); + void performCallback(uint proc, Addr address); + + private: + InvalidateGeneratorStatus m_status; + Addr m_address; + uint m_active_read_node; + uint m_active_inv_node; + uint m_addr_increment_size; +}; + +#endif //__CPU_DIRECTEDTEST_INVALIDATEGENERATOR_HH__ + diff --git a/src/cpu/testers/directedtest/RubyDirectedTester.cc b/src/cpu/testers/directedtest/RubyDirectedTester.cc new file mode 100644 index 000000000..56352d14a --- /dev/null +++ b/src/cpu/testers/directedtest/RubyDirectedTester.cc @@ -0,0 +1,136 @@ +/* + * Copyright (c) 1999-2008 Mark D. Hill and David A. Wood + * Copyright (c) 2009-2010 Advanced Micro Devices, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer; + * redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution; + * neither the name of the copyright holders nor the names of its + * contributors may be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include "cpu/testers/directedtest/DirectedGenerator.hh" +#include "cpu/testers/directedtest/RubyDirectedTester.hh" +#include "mem/ruby/eventqueue/RubyEventQueue.hh" +#include "sim/sim_exit.hh" + +RubyDirectedTester::RubyDirectedTester(const Params *p) + : MemObject(p), directedStartEvent(this), + m_requests_to_complete(p->requests_to_complete), + generator(p->generator) +{ + m_requests_completed = 0; + + // add the check start event to the event queue + schedule(directedStartEvent, 1); +} + +RubyDirectedTester::~RubyDirectedTester() +{ + for (int i = 0; i < ports.size(); i++) + delete ports[i]; +} + +void +RubyDirectedTester::init() +{ + assert(ports.size() > 0); + generator->setDirectedTester(this); +} + +Port * +RubyDirectedTester::getPort(const std::string &if_name, int idx) +{ + if (if_name != "cpuPort") { + panic("RubyDirectedTester::getPort: unknown port %s requested", if_name); + } + + if (idx >= (int)ports.size()) { + ports.resize(idx + 1); + } + + if (ports[idx] != NULL) { + panic("RubyDirectedTester::getPort: port %d already assigned", idx); + } + + CpuPort *port = new CpuPort(csprintf("%s-port%d", name(), idx), this, idx); + + ports[idx] = port; + return port; +} + +Tick +RubyDirectedTester::CpuPort::recvAtomic(PacketPtr pkt) +{ + panic("RubyDirectedTester::CpuPort::recvAtomic() not implemented!\n"); + return 0; +} + +bool +RubyDirectedTester::CpuPort::recvTiming(PacketPtr pkt) +{ + tester->hitCallback(idx, pkt->getAddr()); + + // + // Now that the tester has completed, delete the packet, then return + // + delete pkt->req; + delete pkt; + return true; +} + +Port* +RubyDirectedTester::getCpuPort(int idx) +{ + assert(idx >= 0 && idx < ports.size()); + + return ports[idx]; +} + +void +RubyDirectedTester::hitCallback(NodeID proc, Addr addr) +{ + DPRINTF(DirectedTest, + "completed request for proc: %d addr: 0x%x\n", + proc, + addr); + + generator->performCallback(proc, addr); + schedule(directedStartEvent, curTick); +} + +void +RubyDirectedTester::wakeup() +{ + if (m_requests_completed < m_requests_to_complete) { + if (!generator->initiate()) { + schedule(directedStartEvent, curTick + 1); + } + } else { + exitSimLoop("Ruby DirectedTester completed"); + } +} + +RubyDirectedTester * +RubyDirectedTesterParams::create() +{ + return new RubyDirectedTester(this); +} diff --git a/src/cpu/testers/directedtest/RubyDirectedTester.hh b/src/cpu/testers/directedtest/RubyDirectedTester.hh new file mode 100644 index 000000000..bd3989c04 --- /dev/null +++ b/src/cpu/testers/directedtest/RubyDirectedTester.hh @@ -0,0 +1,118 @@ +/* + * Copyright (c) 1999-2008 Mark D. Hill and David A. Wood + * Copyright (c) 2009-2010 Advanced Micro Devices, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer; + * redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution; + * neither the name of the copyright holders nor the names of its + * contributors may be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef __CPU_DIRECTEDTEST_RUBYDIRECTEDTESTER_HH__ +#define __CPU_DIRECTEDTEST_RUBYDIRECTEDTESTER_HH__ + +#include <iostream> +#include <vector> +#include <string> + +#include "mem/mem_object.hh" +#include "mem/packet.hh" +#include "mem/ruby/common/DataBlock.hh" +#include "mem/ruby/common/Global.hh" +#include "mem/ruby/common/SubBlock.hh" +#include "mem/ruby/system/RubyPort.hh" +#include "params/RubyDirectedTester.hh" + +class DirectedGenerator; + +class RubyDirectedTester : public MemObject +{ + public: + class CpuPort : public SimpleTimingPort + { + private: + RubyDirectedTester *tester; + + public: + CpuPort(const std::string &_name, RubyDirectedTester *_tester, uint _idx) + : SimpleTimingPort(_name, _tester), tester(_tester), idx(_idx) + {} + + uint idx; + + protected: + virtual bool recvTiming(PacketPtr pkt); + virtual Tick recvAtomic(PacketPtr pkt); + }; + + typedef RubyDirectedTesterParams Params; + RubyDirectedTester(const Params *p); + ~RubyDirectedTester(); + + virtual Port *getPort(const std::string &if_name, int idx = -1); + + Port* getCpuPort(int idx); + + virtual void init(); + + void wakeup(); + + void incrementCycleCompletions() { m_requests_completed++; } + + void printStats(std::ostream& out) const {} + void clearStats() {} + void printConfig(std::ostream& out) const {} + + void print(std::ostream& out) const; + + protected: + class DirectedStartEvent : public Event + { + private: + RubyDirectedTester *tester; + + public: + DirectedStartEvent(RubyDirectedTester *_tester) + : Event(CPU_Tick_Pri), tester(_tester) + {} + void process() { tester->wakeup(); } + virtual const char *description() const { return "Directed tick"; } + }; + + DirectedStartEvent directedStartEvent; + + private: + void hitCallback(NodeID proc, Addr addr); + + void checkForDeadlock(); + + // Private copy constructor and assignment operator + RubyDirectedTester(const RubyDirectedTester& obj); + RubyDirectedTester& operator=(const RubyDirectedTester& obj); + + uint64 m_requests_completed; + std::vector<CpuPort*> ports; + uint64 m_requests_to_complete; + DirectedGenerator* generator; +}; + +#endif // __CPU_DIRECTEDTEST_RUBYDIRECTEDTESTER_HH__ diff --git a/src/cpu/testers/directedtest/RubyDirectedTester.py b/src/cpu/testers/directedtest/RubyDirectedTester.py new file mode 100644 index 000000000..af1970594 --- /dev/null +++ b/src/cpu/testers/directedtest/RubyDirectedTester.py @@ -0,0 +1,52 @@ +# Copyright (c) 2010 Advanced Micro Devices, Inc. +# All rights reserved. +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions are +# met: redistributions of source code must retain the above copyright +# notice, this list of conditions and the following disclaimer; +# redistributions in binary form must reproduce the above copyright +# notice, this list of conditions and the following disclaimer in the +# documentation and/or other materials provided with the distribution; +# neither the name of the copyright holders nor the names of its +# contributors may be used to endorse or promote products derived from +# this software without specific prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +# +# Authors: Brad Beckmann + +from m5.SimObject import SimObject +from MemObject import MemObject +from m5.params import * +from m5.proxy import * + +class DirectedGenerator(SimObject): + type = 'DirectedGenerator' + abstract = True + num_cpus = Param.Int("num of cpus") + +class SeriesRequestGenerator(DirectedGenerator): + type = 'SeriesRequestGenerator' + addr_increment_size = Param.Int(64, "address increment size") + issue_writes = Param.Bool(True, "issue writes if true, otherwise reads") + +class InvalidateGenerator(DirectedGenerator): + type = 'InvalidateGenerator' + addr_increment_size = Param.Int(64, "address increment size") + +class RubyDirectedTester(MemObject): + type = 'RubyDirectedTester' + cpuPort = VectorPort("the cpu ports") + requests_to_complete = Param.Int("checks to complete") + generator = Param.DirectedGenerator("the request generator") diff --git a/src/cpu/testers/directedtest/SConscript b/src/cpu/testers/directedtest/SConscript new file mode 100644 index 000000000..1afa15984 --- /dev/null +++ b/src/cpu/testers/directedtest/SConscript @@ -0,0 +1,48 @@ +# -*- mode:python -*- + +# Copyright (c) 2006 The Regents of The University of Michigan +# Copyright (c) 2009-2010 Advanced Micro Devices, Inc. +# All rights reserved. +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions are +# met: redistributions of source code must retain the above copyright +# notice, this list of conditions and the following disclaimer; +# redistributions in binary form must reproduce the above copyright +# notice, this list of conditions and the following disclaimer in the +# documentation and/or other materials provided with the distribution; +# neither the name of the copyright holders nor the names of its +# contributors may be used to endorse or promote products derived from +# this software without specific prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +# + +Import('*') + +# +# Currently the ruby testser relies on Ruby specific objects (SubBlock, etc.) +# When this dependency is removed, the ruby tester should be compiled +# independently from Ruby +# +if not env['RUBY']: + Return() + +SimObject('RubyDirectedTester.py') + +Source('RubyDirectedTester.cc') +Source('DirectedGenerator.cc') +Source('SeriesRequestGenerator.cc') +Source('InvalidateGenerator.cc') + +TraceFlag('DirectedTest') diff --git a/src/cpu/testers/directedtest/SeriesRequestGenerator.cc b/src/cpu/testers/directedtest/SeriesRequestGenerator.cc new file mode 100644 index 000000000..5b6395f93 --- /dev/null +++ b/src/cpu/testers/directedtest/SeriesRequestGenerator.cc @@ -0,0 +1,114 @@ +/* + * Copyright (c) 1999-2008 Mark D. Hill and David A. Wood + * Copyright (c) 2009-2010 Advanced Micro Devices, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer; + * redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution; + * neither the name of the copyright holders nor the names of its + * contributors may be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include "cpu/testers/directedtest/DirectedGenerator.hh" +#include "cpu/testers/directedtest/RubyDirectedTester.hh" +#include "cpu/testers/directedtest/SeriesRequestGenerator.hh" + +SeriesRequestGenerator::SeriesRequestGenerator(const Params *p) + : DirectedGenerator(p) +{ + m_status = SeriesRequestGeneratorStatus_Thinking; + m_active_node = 0; + m_address = 0x0; + m_addr_increment_size = p->addr_increment_size; + m_issue_writes = p->issue_writes; +} + +SeriesRequestGenerator::~SeriesRequestGenerator() +{ +} + +bool +SeriesRequestGenerator::initiate() +{ + DPRINTF(DirectedTest, "initiating request\n"); + assert(m_status == SeriesRequestGeneratorStatus_Thinking); + + RubyDirectedTester::CpuPort* port = + safe_cast<RubyDirectedTester::CpuPort*>(m_directed_tester-> + getCpuPort(m_active_node)); + + Request::Flags flags; + + // For simplicity, requests are assumed to be 1 byte-sized + Request *req = new Request(m_address, 1, flags); + + Packet::Command cmd; + if (m_issue_writes) { + cmd = MemCmd::WriteReq; + } else { + cmd = MemCmd::ReadReq; + } + PacketPtr pkt = new Packet(req, cmd, m_active_node); + uint8_t* dummyData = new uint8_t; + *dummyData = 0; + pkt->dataDynamic(dummyData); + + if (port->sendTiming(pkt)) { + DPRINTF(DirectedTest, "initiating request - successful\n"); + m_status = SeriesRequestGeneratorStatus_Request_Pending; + return true; + } else { + // If the packet did not issue, must delete + // Note: No need to delete the data, the packet destructor + // will delete it + delete pkt->req; + delete pkt; + + DPRINTF(DirectedTest, "failed to initiate request - sequencer not ready\n"); + return false; + } +} + +void +SeriesRequestGenerator::performCallback(uint proc, Addr address) +{ + assert(m_active_node == proc); + assert(m_address == address); + assert(m_status == SeriesRequestGeneratorStatus_Request_Pending); + + m_status = SeriesRequestGeneratorStatus_Thinking; + m_active_node++; + if (m_active_node == m_num_cpus) { + // + // Cycle of requests completed, increment cycle completions and restart + // at cpu zero + // + m_directed_tester->incrementCycleCompletions(); + m_address += m_addr_increment_size; + m_active_node = 0; + } +} + +SeriesRequestGenerator * +SeriesRequestGeneratorParams::create() +{ + return new SeriesRequestGenerator(this); +} diff --git a/src/cpu/testers/directedtest/SeriesRequestGenerator.hh b/src/cpu/testers/directedtest/SeriesRequestGenerator.hh new file mode 100644 index 000000000..97b632a12 --- /dev/null +++ b/src/cpu/testers/directedtest/SeriesRequestGenerator.hh @@ -0,0 +1,63 @@ +/* + * Copyright (c) 1999-2008 Mark D. Hill and David A. Wood + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer; + * redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution; + * neither the name of the copyright holders nor the names of its + * contributors may be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +// +// This Deterministic Generator generates GETX requests for all nodes in the +// system. The GETX requests are generated one at a time in round-robin fashion +// 0...1...2...etc. +// + +#ifndef __CPU_DIRECTEDTEST_SERIESREQUESTGENERATOR_HH__ +#define __CPU_DIRECTEDTEST_SERIESREQUESTGENERATOR_HH__ + +#include "cpu/testers/directedtest/DirectedGenerator.hh" +#include "cpu/testers/directedtest/RubyDirectedTester.hh" +#include "mem/protocol/SeriesRequestGeneratorStatus.hh" +#include "params/SeriesRequestGenerator.hh" + +class SeriesRequestGenerator : public DirectedGenerator +{ + public: + typedef SeriesRequestGeneratorParams Params; + SeriesRequestGenerator(const Params *p); + + ~SeriesRequestGenerator(); + + bool initiate(); + void performCallback(uint proc, Addr address); + + private: + SeriesRequestGeneratorStatus m_status; + Addr m_address; + uint m_active_node; + uint m_addr_increment_size; + bool m_issue_writes; +}; + +#endif //__CPU_DIRECTEDTEST_SERIESREQUESTGENERATOR_HH__ + |