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-rw-r--r--src/cpu/testers/directedtest/InvalidateGenerator.cc4
-rw-r--r--src/cpu/testers/directedtest/SeriesRequestGenerator.cc2
2 files changed, 3 insertions, 3 deletions
diff --git a/src/cpu/testers/directedtest/InvalidateGenerator.cc b/src/cpu/testers/directedtest/InvalidateGenerator.cc
index f01e6fb50..4c248ea05 100644
--- a/src/cpu/testers/directedtest/InvalidateGenerator.cc
+++ b/src/cpu/testers/directedtest/InvalidateGenerator.cc
@@ -68,13 +68,13 @@ InvalidateGenerator::initiate()
cmd = MemCmd::ReadReq;
port = safe_cast<RubyDirectedTester::CpuPort*>(m_directed_tester->
getCpuPort(m_active_read_node));
- pkt = new Packet(req, cmd, m_active_read_node);
+ pkt = new Packet(req, cmd);
} else if (m_status == InvalidateGeneratorStatus_Inv_Waiting) {
DPRINTF(DirectedTest, "initiating invalidating write\n");
cmd = MemCmd::WriteReq;
port = safe_cast<RubyDirectedTester::CpuPort*>(m_directed_tester->
getCpuPort(m_active_inv_node));
- pkt = new Packet(req, cmd, m_active_inv_node);
+ pkt = new Packet(req, cmd);
} else {
panic("initiate was unexpectedly called\n");
}
diff --git a/src/cpu/testers/directedtest/SeriesRequestGenerator.cc b/src/cpu/testers/directedtest/SeriesRequestGenerator.cc
index 137d24b21..92dc46f85 100644
--- a/src/cpu/testers/directedtest/SeriesRequestGenerator.cc
+++ b/src/cpu/testers/directedtest/SeriesRequestGenerator.cc
@@ -67,7 +67,7 @@ SeriesRequestGenerator::initiate()
} else {
cmd = MemCmd::ReadReq;
}
- PacketPtr pkt = new Packet(req, cmd, m_active_node);
+ PacketPtr pkt = new Packet(req, cmd);
uint8_t* dummyData = new uint8_t;
*dummyData = 0;
pkt->dataDynamic(dummyData);