diff options
Diffstat (limited to 'src/cpu/testers/rubytest/RubyTester.hh')
-rw-r--r-- | src/cpu/testers/rubytest/RubyTester.hh | 32 |
1 files changed, 27 insertions, 5 deletions
diff --git a/src/cpu/testers/rubytest/RubyTester.hh b/src/cpu/testers/rubytest/RubyTester.hh index b24dddd83..82698f201 100644 --- a/src/cpu/testers/rubytest/RubyTester.hh +++ b/src/cpu/testers/rubytest/RubyTester.hh @@ -51,11 +51,28 @@ class RubyTester : public MemObject RubyTester *tester; public: - CpuPort(const std::string &_name, RubyTester *_tester, int _idx) - : MasterPort(_name, _tester), tester(_tester), idx(_idx) + // + // Currently, each instatiation of the RubyTester::CpuPort supports + // only instruction or data requests, not both. However, for those + // RubyPorts that support both types of requests, separate InstOnly + // and DataOnly CpuPorts will map to that RubyPort + // + enum Type + { + // Port supports only instruction requests + InstOnly, + // Port supports only data requests + DataOnly + }; + + CpuPort(const std::string &_name, RubyTester *_tester, int _idx, + Type _type) + : MasterPort(_name, _tester), tester(_tester), idx(_idx), + type(_type) {} int idx; + Type type; protected: virtual bool recvTiming(PacketPtr pkt); @@ -90,7 +107,8 @@ class RubyTester : public MemObject virtual MasterPort &getMasterPort(const std::string &if_name, int idx = -1); - MasterPort* getCpuPort(int idx); + MasterPort* getReadableCpuPort(int idx); + MasterPort* getWritableCpuPort(int idx); virtual void init(); @@ -136,13 +154,17 @@ class RubyTester : public MemObject CheckTable* m_checkTable_ptr; std::vector<Time> m_last_progress_vector; + int m_num_cpus; uint64 m_checks_completed; - std::vector<CpuPort*> ports; + std::vector<CpuPort*> writePorts; + std::vector<CpuPort*> readPorts; uint64 m_checks_to_complete; int m_deadlock_threshold; - int m_num_cpu_sequencers; + int m_num_writers; + int m_num_readers; int m_wakeup_frequency; bool m_check_flush; + int m_num_inst_ports; }; inline std::ostream& |