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-rw-r--r--src/cpu/testers/traffic_gen/base_gen.hh40
1 files changed, 38 insertions, 2 deletions
diff --git a/src/cpu/testers/traffic_gen/base_gen.hh b/src/cpu/testers/traffic_gen/base_gen.hh
index 5f1c2afd9..b7c3363ff 100644
--- a/src/cpu/testers/traffic_gen/base_gen.hh
+++ b/src/cpu/testers/traffic_gen/base_gen.hh
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2012-2013, 2017 ARM Limited
+ * Copyright (c) 2012-2013, 2017-2018 ARM Limited
* All rights reserved
*
* The license below extends only to copyright in the software and shall
@@ -52,6 +52,8 @@
#include "base/intmath.hh"
#include "mem/packet.hh"
+class BaseTrafficGen;
+
/**
* Base class for all generators, with the shared functionality and
* virtual functions for entering, executing and leaving the
@@ -68,6 +70,9 @@ class BaseGen
/** The MasterID used for generating requests */
const MasterID masterID;
+ /** Cache line size in the simulated system */
+ const Addr cacheLineSize;
+
/**
* Generate a new request and associated packet
*
@@ -91,7 +96,7 @@ class BaseGen
* @param master_id MasterID set on each request
* @param _duration duration of this state before transitioning
*/
- BaseGen(const std::string& _name, MasterID master_id, Tick _duration);
+ BaseGen(BaseTrafficGen &gen, Tick _duration);
virtual ~BaseGen() { }
@@ -132,4 +137,35 @@ class BaseGen
};
+class StochasticGen : public BaseGen
+{
+ public:
+ StochasticGen(BaseTrafficGen &gen, Tick _duration,
+ Addr start_addr, Addr end_addr, Addr _blocksize,
+ Tick min_period, Tick max_period,
+ uint8_t read_percent, Addr data_limit);
+
+ protected:
+ /** Start of address range */
+ const Addr startAddr;
+
+ /** End of address range */
+ const Addr endAddr;
+
+ /** Blocksize and address increment */
+ const Addr blocksize;
+
+ /** Request generation period */
+ const Tick minPeriod;
+ const Tick maxPeriod;
+
+ /**
+ * Percent of generated transactions that should be reads
+ */
+ const uint8_t readPercent;
+
+ /** Maximum amount of data to manipulate */
+ const Addr dataLimit;
+};
+
#endif